28
LatticeMico32/DSP Development Board
Lattice Semiconductor
User’s Guide
G18
HS DAT1+
High-speed LVDS Connector
J22
HS DAT3-
High-speed LVDS Connector
J21
HS DAT3+
High-speed LVDS Connector
E21
HS DAT0-
High-speed LVDS Connector
D22
HS DAT0+
High-speed LVDS Connector
L4
I2C SCL1
I
2
C
L5
I2C SDA1
I
2
C
R20
JTAG DONE
Configuration
T21
JTAG INIT
Configuration
P5
LCD ENABLE
LCD
P3
LCD REGSEL
LCD
P4
LCD RW
LCD
E3
LED0#
LED
E4
LED1#
LED
E5
LED2#
LED
F4
LED3#
LED
F5
LED4#
LED
G4
LED5#
LED
G5
LED6#
LED
H5
LED7#
LED
B1
MACHXO CLK0
Configuration
C1
MACHXO IO0
Configuration
E2
MACHXO IO1
Configuration
F3
MACHXO IO2
Configuration
R6
MACHXO IO3
Configuration
U3
MACHXO IO4
Configuration
V3
MACHXO IO5
Configuration
V2
MACHXO IO6
Configuration
V1
CLK FPGA
Clock
AB20
MEMORY A0
FLASH/SRAM
AA20
MEMORY A1
FLASH/SRAM
AA17
MEMORY A10
FLASH/SRAM
Y17
MEMORY A11
FLASH/SRAM
W17
MEMORY A12
FLASH/SRAM
V17
MEMORY A13
FLASH/SRAM
U17
MEMORY A14
FLASH/SRAM
AB16
MEMORY A15
FLASH/SRAM
AA16
MEMORY A16
FLASH/SRAM
Y16
MEMORY A17
FLASH/SRAM
W16
MEMORY A18
FLASH/SRAM
V16
MEMORY A19
FLASH/SRAM
AB19
MEMORY A2
FLASH/SRAM
U16
MEMORY A20
FLASH/SRAM
AB15
MEMORY A21
FLASH/SRAM
Table 25. Pin Table (Continued)
Pin Name
Signal Name
Appliance