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ECP5 and ECP5-5G High-Speed I/O Interface

Technical Note

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FPGA-TN-02035-1.3

ECP5 and ECP5-5G Memory Interfaces

All of the DDR SDRAM interface transfers data at both the rising and falling edges of the clock. The I/O DDR registers in
the ECP5 and ECP5-5G device can be used to support DDR2, DDR3, DDR3L, LPDDR2, and LPDDR3 memory interfaces.

These memory interfaces rely on the use of a data strobe signal, called DQS, for high-speed operation. The DQS strobe
is a differential signal except for DDR2 you can choose between single-ended or differential DQS strobe.

Figure 6.1

shows typical DDR memory signals. DDR2, DDR3, and DDR3L memory interfaces are typically implemented

with either four or eight DQ data bits per DQS. So, a 16-bit DDR memory interface uses two or four DQS signals, and
each DQS is associated with four or eight DQ bits, respectively. Both the DQ and DQS are bi-directional ports and are
used to read and write to the memory. LPDDR2 and LPDDR3 memory are the same but only supports 8 DQ data bits per
DQS strobe.

When reading data from the external memory device, data coming into the FPGA controller is edge-aligned with
respect to the DQS signal. This DQS strobe signal needs to be phase shifted 90° before the FPGA logic can sample the
read data. When writing to a DDR memory, the memory controller (FPGA) must shift the DQS by 90° to center-align
with the data signals (DQ). A clock signal is also provided to the memory. This clock is provided as differential clock (CK
and CK#) to minimize duty cycle variations. The memory also uses these clock signals to generate the DQS signal during
a read via a DLL inside the memory. The figures below show DQ and DQS timing relationships for read and write cycles.

During read, the DQS signal is low for some duration after it comes out of tristate. This state is called Preamble.

The state when the DQS is low before it goes into tristate is the Postamble state. This is the state after the last valid
data transition.

DDR memories also require a Data Mask (DM) signal to mask data bits during write cycles. Note that the ratio of DQS to
data bits is independent of the overall width of the memory.

Figure 6.1

shows a typical 8-bit interface that has eight

associated DQ data bits per DQS strobe signal.

The DDR3 memory module uses fly-by routing topology for the address, command, control, and clock signals. This
requires the memory controller to support read and write leveling to adjust for leveled delay on read and write data
transfers. LPDDR3 does not use fly-by routing but write leveling may be supported if you emulate the fly-by routing
using board traces. You can see more information in the DDR pin placement and layout guidelines section of this
document.

One major difference between DDR2/DDR3 and LPDDR2/LPDDR3 is lack of DLL in LPDDR2/LPDDR3 memory device. This
would mean in LPDDR2 and LPDDR3, the clock to data output delay from memory device is not compensated by DLL as
in traditional DDR2/DDR3, thus the delay is much larger and has larger spread. Theoretically, there is no low frequency
limitation on LPDDR2/LPDDR3, although most manufactures place a low limit of 10 MHz. Please note FPGA memory
controller side, DLL is still needed to manage write and read phase shift, for all memory interfaces including LPDDR2
and LPDDR3.

FPGA

(DDR Memory Controller)

DQ[7:0]

DQS/DQS#

ADDR, BA

CASN, RASN, WEN

CKE, ODT, CSN

CK/CK#

DDR Memory

DQ[7:0]

DQS/DQS#

ADDR, BA