ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
FPGA-TN-02035-1.3
5.12.2.
Receive Interface Guidelines
Differential DDR interface can be implemented on the Left and Right sides of the device.
There are four different Edge Clocks available per side (two per bank).
Each of the Edge Clocks can be used to generate either a centered of aligned interface.
Each side has two CLKDIV modules which would mean you can implement two different GDDRX2 RX interface per
side since each 2x gearing would require CLKDIV module to generate a slower SCLK.
There is DDRDLLA located on each corner of the device, total of four in a device. LLC and LRC DDRDLLs only drive
code to one side whereas the ULC and URC DDRDLLs drive code to two sides turning corners.
Each DQSBUF/DLLDEL has access to two DDRDLLs hence two different RX rates are available per side, 4 are
available on the entire device.
The Receive clock input should be placed on a dedicated PCLK input pin. The PCLK pin has direct access to the Edge
Clock tree for centered interface and it also has direct connection to the DLLDELD when implementing an aligned
interface.
When implementing IDDRX71 interface, the complementary PAD is not available for other functions since the
IDDRX71 used the I/O registers of the complementary PAD as well.
It is recommended that clock input is located on the same side as data pins.
The top side of the device does not have Edge Clocks hence can only be used to receive lower speed interfaces
(<200 MHz) that use 1x gearing. Top side of the device can be used for single ended interfaces only.
Interfaces using the x1 gearing uses the primary clock resource. You can use as many interfaces as the number of
primary clocks supported in the device.
5.12.3.
Transmit interface Guidelines
Use PADA and PADB for all TX using true LVDS interfaces.
When implementing Transmit Centered interface, two ECLKs are required. One is to generate the data output and
the other is to generate the CLK output.
When implementing Transmit Aligned interface only one ECLK is required for both data output and clock output.
Each side has two CLKDIV modules which would mean you can implement two different GDDRX2 TX interface per
side since each 2x gearing would require CLKDIV module to generate a slower SCLK.
The top side of the device does not have Edge Clocks. Hence, it can only be used to receive lower speed interfaces
(<200 MHz) that use 1x gearing. Top side of the device can be used for single ended interfaces only.
Interfaces using the x1 gearing uses the primary clock resource. You can use as many interfaces as the number of
primary clocks supported in the device.
5.12.4.
Clocking Guidelines for Generic DDR Interface
The Edge Clock and Primary Clock resources are used when implementing a 2x receive or transmit interface.
Only the Primary Clock (PCLK) resources are used when implementing x1 receive or transmit interfaces.
Each Edge Clock can only span up to one side (Left or Right) of the device, hence all the data bits of the in the x2
interface must be locked to one side of the device. If wide bus implementation is required, then the ECLKBRIDGE
element must be used to bridge the Edge Clock to the other side. ECLKBRIDGE can be used to bridge the Left and
Right Side ECLKs.
When implementing x1 interfaces, the bus can span Left, Right or Top sides as primary clocks can access DDR
registers on all sides.
Bottom side only supports SERDES function hence does not have any Edge Clocks or DDR registers except on the
LFE-85 device, some I/O support 1x DDR registers similar to the Top side.
The ECLK to DDR registers can be accessed through dedicated PCLK pins, GPLL outputs, DDRDLL outputs. See
and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200)
Primary Clock to DDR registers can be accessed through dedicated PCLK pins, GPLL outputs and CLKDIV outputs.
See
ECP5 and ECP5-5G sysClock PLL/DLL Design and Usage Guide (FPGA-TN-02200)
None of the clocks going to the DDR registers can come from internal general routing.
