Lattice Semiconductor CrossLink LIF-MD6000, User Manual

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CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
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FPGA-EB-02010-1.4 15
Table 7.3. J2 Header Description
Pin Name Mapping to U1
1 +3.3V N/A
2 +1.8V N/A
3 RESETN Pin 22
4 CH4_DCK_TX_P Pin 1
5 SDA Pin 39
6 CH4_DCK_TX_N Pin 2
7 SCL Pin 40
8 GND N/A
9 GND N/A
10 CH4_DATA0_TX_P Pin 4
11 CH4_DATA3_TX_P Pin 16
12 CH4_DATA0_TX_N Pin 5
13 CH4_DATA3_TX_N Pin 17
14 GND N/A
15 GND N/A
16 CH4_DATA1_TX_P Pin 7
17 CH4_DATA4_TX_P Pin 24
18 CH4_DATA1_TX_N Pin 8
19 CH4_DATA4_TX_N Pin 25
20 GND N/A
21 GND N/A
22 CH4_DATA2_TX_P Pin 13
23 CH4_DATA5_TX_P Pin 27
24 CH4_DATA2_TX_N Pin 14
25 CH4_DATA5_TX_N Pin 28
26 GND N/A