Lattice Semiconductor CrossLink LIF-MD6000, User Manual

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CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 37
Revision History
Date Version Change Summary
April 2018 1.4 Made schematics searchable.
March 2018 1.3 Added footnote to Table 2.1.
September 2017 1.2

Changed document number from EB105 to FPGA-EB-02010.

Changed J25 from VCCIO1 to VCCIO2 in Table 2.1. Headers and Test Connectors.

Updated 100MILS_DEBUG Header in Appendix E. B-IOL-EVN-BRD Schematics.
April 2017 1.1 New sections:

SMA IO Link Board

Breakout IO Link Board

Ordering Information
Updated Appendix A. LIF-MD6000-ML-EVN-BRD Schematics:

Changed “SW4 SYS_RST” to “SW4 EXT_RST” in the Bank 1, 2 – LVDS Rx diagram.

Changed “EXTERNAL RESET” to “SYSTEM RESET” in the Bank0, Flash Interface
diagram.
May 2016 1.0 Initial release.