CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
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10
FPGA-EB-02010-1.4
Table 4.2. Device Power Rail Summary and Test Points
Voltage Rail
Source Rail
Current Sense Resistor
Test Points
12 V
12_Ext
—
12V
5 V
12 V
—
5V
+3.3 V
5 V
—
3V3
+2.5 V
5 V
—
2V5
+1.8 V
5 V
—
1V8
+1.2 V
5 V
—
1V2
VCCCORE
+1.2 V
R19
VCC_CORE
VCCIO0
+3.3 V
R20
VCCIO0
VCCIO1
+3.3 V
R21
VCCIO1
VCCIO2
+3.3 V
R28
VCCIO2
VCC_DPHY
+1.2 V
R417
VCC_DPHY
1K_VCC_CORE
1.2 V
R190
1K_VCC_CORE
1K_VCCIO0
+3.3 V
R410
1K_VCCIO0
1K_VCCIO1
+3.3 V
R184
1K_VCCIO1
1K_VCCIO2
+3.3 V
R186
1K_VCCIO2
1K_VCCIO3
+3.3 V
R188
1K_VCCIO3
