Lattice Semiconductor CrossLink LIF-MD6000, User Manual

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CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02010-1.4
2. Headers and Test Connections
Figure 1.1 shows the top view of the Master Link board. The headers and test connections on the board provide access
to LIF-MD6000 Master Link demo board circuits. Table 2.1 lists the headers and test connectors.
Table 2.1. Headers and Test Connectors
Part Description Setting
J1 External JTAG interface - For LCMX03 only —
J8 External 12 V terminal block Open
J9 External 5 V terminal block Open
SW1 External adaptor power ON/OFF —
J22 External reference clock input for MIPI D-PHY reference clock —
J21 External or internal reference clock selection 1–2 (External), 2–3 (Internal)
J5 Debug I/O —
J20 LIF-MD6000 chip select OPEN-OFF, SHORT-ON
J19 SPI Flash chip select OPEN-OFF, SHORT-ON
J4 External clock input for MIPI D-PHY reference clock —
J6 External or internal clock selection 1–2 (External), 2–3 (Internal)
J18 External SP/I
2
C access —
SW2 Configuration reset for LIF-MD6000 —
J29 Reset signal voltage selector 1-2 (VCCIO2), 2-3 (VCCIO0)
J28 Reveal analyzer signal connector —
J26 Internal/External clock and I2C SDA Mux 1-2 (CLK_INT), 2-3 (CLK_EXT), 2-4 (SDA)
J27 Internal/External reference clock and I2C SCL Mux 1-2 (CLK_INT_REF), 2-3 (CLK_EXT_REF), 2-4 (SCL)
J24 VCCIO1 Bank voltage selector 1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J25 VCCIO2 Bank voltage selector 1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J3 External power jack —
U7, U9 Tx Connectors for external interface —
U11, U12 Rx Connectors for external interface —
SW4* External reset for LIF-MD6000 device —
SW3 External reset for LCMXO3L device —
SW5 PMU WAKEUP Switch —
J23 Debug Header for LCMXO3L device —
*Note : Some CrossLink demos utilize this reset signal to ball G9 of Bank 2 while it is configured as a 1.2 V Bank. However, LVCMOS12
inputs are no longer supported across all 3 Banks. Lattice Diamond ® Software 3.9 and later will not allow this signal to be placed on a
1.2 V Bank. If it is necessary to recompile one of these demo projects, the necessary modifications should be made to the project
and the board to move this reset signal to a non-1.2 V Bank on CrossLink.