CertusPro-NX SerDes/PCS Usage Guide
Preliminary
Technical Note
86
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FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Port Name
Width
Description
lmmi_resetn_i
NL
Active Low LMMI Reset.
Power Control Signals
mpcs_pwrdn_i
2*NL
This signal is used to put PMA in power down mode. This signal has
only three states. Exists only in MPCS mode.
2’b11 – deep low-power state.
2’b10 – low-power state.
2’b00 – operational state.
epcs_pwrdn_i
2*NL
This signal is used to put PMA in power down mode. This signal has
only three states. Exists only in PMA Only mode.
2’b11 – deep low-power state.
2’b10 – low-power state.
2’b00 – operational state.
Reset Sequence
This section covers the recommended reset sequence for MPCS mode and PMA Only mode. For reset sequence
required by PIPE mode and PCI Express Hard IP mode, refer to CertusPro-NX PCI Express Hardened IP Core User Guide
(FPGA-IPUG-
XXXXX
).
7.7.2.1.
MPCS Mode
shows the MPCS mode reset sequence timing diagram for Tx path.
After power up, the valid and stable clocks should be connected to lmmi_clk_i and mpcs_clkin_i ports. Then
lmmi_resetn_i should be released by user logic to allow INIT bus to start PMA and PCS register initialization. During
stage A, main power is applied to the SerDes/PCS and no clock is valid yet. All reset signal should be asserted by user
logic.
User logic can release mpcs_resetn_i to inform SerDes/PCS module that user logic is ready and no more registers need
to be configured from user logic, which requires PMA and PMA Controller under the reset state. During stage B, PMA,
PMA Controller, and MPCS are under the reset state, but register access bus is working. After mpcs_resetn_i is released
by user logic, SerDes/PCS module checks whether or not all the following conditions are satisfied. Then, SerDes/PCS
module can decide if PMA and PMA Controller reset should be released.
Channel PMA analog powers (VCCSDx and VCCPLLSDx) are stable.
Global Set/Reset (GSR) has been released by configuration module.
Reference clock is ready and stable.
During stage C, mpcs_tx_out_clk can be available but not accurate when Tx PLL locks on the reference clock. PMA
Controller works with PMA on calibration, mpcs_ready_o asserts when PMA calibration is done. PMA calibration may
fail if there are some issues on the external PMA PLL filter. Refer to
for detailed requirements about the
PMA PLL filter. What should be noted is that it is forbidden to write any PMA registers during stage C.
Once mpcs_ready_o is asserted, user logic can assert mpcs_txval_i to let PMA quit electrical idle state. Finally, user
logic can release mpcs_tx_pcs_rstn_i and put valid data onto mpcs_tx_ch_din_i port.
During stage F, PMA, PMA Controller and MPCS are in the normal working mode and are ready to transmit data.
shows the MPCS mode reset sequence timing diagram for Rx path.
Reset sequence timing for Rx path is the same as the timing for Tx path during stage A and stage B.
During stage C, mpcs_rx_out_clk can be available but not accurate when Rx CDR PLL locks on the reference clock.
During stage D, Rx CDR PLL is trying to lock on input data stream. mpcs_rxval can be asserted once Rx CDR locks on the
input data stream.
User logic can release mpcs_rx_pcs_rstn_i when mpcs_rxval_o has been asserted to receive valid data from
mpcs_rx_ch_dout_o port.
During stage F, PMA, PMA Controller and MPCS are in the normal working mode and are ready to receive data.
