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CertusPro-NX SerDes/PCS Usage Guide

Preliminary

Technical Note

FPGA-TN-02245-0.81

© 2020-2021 Lattice Semiconductor

21

All rights reserved. CONFIDENTIAL

Express PCS block using the PIPE interface with up to 128-bit data width. The Link Layer block operates at the clock
frequency of 250 MHz, while the user interface is at 125 MHz in Gen1/Gen2 speed and 250 MHz in Gen3 speed. The
user interface, TLP interface, can be from 32 bits up to 128 bits wide depending on the core configuration. 32 bits of
the TLP interface is used for ×1 mode, 64 bits of TLP interface is used for ×2 mode, and 128 bits of the TLP interface is
used for ×4 mode.

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PCI Express Link Layer Quad

PCI Express Link

Layer x1 Core

PCI Express Link

Layer x4 Core

Configuration

Space Registers

(x1 + x4)

Buff er

25

0

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32 bits UCFG x4

32 bits TLP (x1)
64 bits TLP (x2)

128 bits TLP (x4)

32 bits LMMI x4

PM

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Figure 5.3. PCI Express Hard IP Architecture

Each PCI Express Link Layer Quad can be configured as x4 mode, x2 mode, x1 mode, x2_x1 mode and x1_x1 mode. In
x2_x1 mode, the Link Layer Quad can support two independent PCI Express applications, one in ×2 mode and the other
in ×1 mode.

describes the SerDes/PCS lane mapping details.

Table 5.4. PCI Express Link Layer Quad Lane Mapping

Mode Name

Description

×4

All 4 lanes are used.

×2

Lane 0 and Lane 1 are used.

×1

Lane 0 is used.

×2_×1

Lane 0 and Lane 1 are used for ×2.
Lane 3 is used for ×1.

×1_×1

Lane 0 and Lane 3 are used for ×1.

shows the PCI Express Link Layer block functional diagram. For more detailed information on CertusPro-NX

PCI Express features, function descriptions, and IP usage, refer to CertusPro-NX PCI Express Hardened IP Core User
Guide (FPGA-IPUG-

XXXXX

).

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Summary of Contents for CertusPro-NX

Page 1: ...CertusPro NX SerDes PCS Usage Guide Preliminary Technical Note FPGA TN 02245 0 81 May 2021...

Page 2: ...rformance specifications or parameters provided herein Products sold by Lattice have been subject to limited testing and it is the Buyer s responsibility to independently determine the suitability of...

Page 3: ...ock Diagram 44 SerDes PCS Function Description 47 SerDes PMA 47 PMA Controller 49 PCI Express PCS 49 MPCS 50 Quad Common 70 Reference Clock 70 Clocks and Reset 72 MPCS Channel Clock Detail 72 MPCS Qua...

Page 4: ...rical Idle 109 Multiple Data Rate Support 109 SerDes PCS Generation in Radiant Software 110 Configuration GUI 110 Attribute Summary 111 Primitive 117 Appendix A Configuration Registers 122 A 1 PMA Reg...

Page 5: ...Case I 54 Figure 6 9 Rx Gearing Case II 55 Figure 6 10 Byte Shifting for Word Alignment Pattern 55 Figure 6 11 Word Aligner Block Diagram 57 Figure 6 12 Link Synchronization FSM 58 Figure 6 13 Before...

Page 6: ...Figure 9 2 8B 10B PCS Near End Parallel Loopback Mode 94 Figure 9 3 8B 10B PCS Far End Parallel Loopback Mode 94 Figure 9 4 64B 66B PCS Loopback Mode 95 Figure 9 5 Signal Detector 95 Figure 9 6 CDR PL...

Page 7: ...le 11 7 DisplayPort Recommend AC Capacitance 104 Table 12 1 Transmit Receive SerDes PCS Latency 105 Table 13 1 Recommended External Reference Resistor for Serval Differential Impedance Applications 10...

Page 8: ...A 46 Word Alignment Pattern Mask Code MSB reg39 139 Table A 47 Sync_Det FSM Configuration 0 reg3a 139 Table A 48 Sync_Det FSM Configuration 1 reg3b 139 Table A 49 Sync_Det FSM Configuration 2 reg3c 13...

Page 9: ...A 99 64B 66B PCS CTC High Water Line Control reg84 147 Table A 100 64B 66B PCS CTC Low Water Line Control reg85 147 Table A 101 64B 66B PCS Block Align Shift reg86 147 Table A 102 10GBASE R BER Count...

Page 10: ...A 131 User Defined BIST Constant 1 MSByte rege5 153 Table A 132 User Defined BIST Constant 2 Byte_0 rege6 154 Table A 133 User Defined BIST Constant 2 Byte_1 rege7 154 Table A 134 User Defined BIST C...

Page 11: ...nt DDR Double Data Rate DFE Decision Feedback Equalization DFF D Flip Flop DP DisplayPort DSP Digital Signal Processor eDP Embedded DisplayPort EI1 Electrical Idle 1 EI2 Electrical Idle 2 EI4 Electric...

Page 12: ...ess PCS Physical Coding Sublayer PFD Phase Frequency Detector PMD Physical Medium Dependent PIPE PHY Interface for PCI Express PISO Parallel In Serial Out PLL Phase Locked Loop PMA Physical Media Atta...

Page 13: ...ata Positive pin TxDN Transmitter Data Negative pin UI Unit Interval USB Universal Serial Bus USB3 USB SuperSpeed VC0_RX Virtual Channel 0 Receiver VC0_TX Virtual Channel 0 Transmitter VESA Video Elec...

Page 14: ...ic inside the CertusPro NX device one is for PCI Express only the other is Multi Protocol Physical Coding Sublayer MPCS for protocols other than PCI Express Each channel of MPCS contains dedicated tra...

Page 15: ...me protocol Minimized Transmitter Tx lane to lane skew Receiver Rx multiple lane de skew up to 100UI Multiple Protocol Clock Tolerance Compensation CTC logic Compensates for frequency difference betwe...

Page 16: ...adiant software The status and control registers associated with the SerDes and PCS logic which can be accessed via the Lattice Memory Mapped Interface LMMI The electrical and timing characteristics o...

Page 17: ...hernet SGMII 1250 125 125 1 8b10b Ethernet XAUI 3125 156 25 156 25 4 8b10b Ethernet QSGMII 5000 125 125 1 8b10b Ethernet 10GBASE R 10312 5 161 1328125 161 1328125 1 64b66b SLVS EC Grade1 1250 125 1 2...

Page 18: ...ll duplex data channels Figure 5 1 shows the arrangement of SerDes PCS Quads on the CertusPro NX 100k device PLL SERDES PCS X4 OSC Configuration Security I O Bank Bank 0 Large RAM ALU ADC 2Ch Large RA...

Page 19: ...tes one PCI Express Link Layer Quad which contains one PCIe 1 block and one PCIe 4 block The PCIe 4 PCI Express Link Layer block can be configured as 1 2 or 4 mode The PCI Express Link Layer block PCI...

Page 20: ...PCI Express Hard IP block The PCI Express Hard IP supports both Endpoint and Root Complex modes It supports up to four physical functions Each of the four functions has independent PCI Express config...

Page 21: ...sters x1 x4 Buffer 250 MHz 250 MHz for Gen3 125 MHz for Gen2 Gen1 32 bits UCFG x4 32 bits TLP x1 64 bits TLP x2 128 bits TLP x4 32 bits LMMI x4 PMA Controller Figure 5 3 PCI Express Hard IP Architectu...

Page 22: ...GMII 10GBASE R SLVS EC CoaXpress and DP eDP MPCS can be configured as Generic 8B 10B mode for user defined serial protocols other than those listed in the Features section Each MPCS Quad includes four...

Page 23: ...industry standard protocols Each Quad and each channel within a Quad can be programmed for many user defined data manipulation modes For example word alignment and clock tolerance compensation can be...

Page 24: ...ed on one reference clock source and the skew between different clock sources The reference clock can source from General purpose PLL GPLL output You can use GPLL to form more clock frequency division...

Page 25: ...share the same SerDes PCS quad Table 5 6 CertusPro NX Mixed Protocols within a Quad Protocol Protocol PCI Express 1000BASE X GigE PCI Express SGMII PCI Express QSGMII PCI Express CoaXPress CXP 1 CXP 2...

Page 26: ...PMA SERDES Channel 2 Rx CDR Tx PLL PMA SERDES Channel 3 Rx CDR Tx PLL Figure 5 9 PIPE Mode For MPCS mode the MPCS interface and LMMI interface are accessible Figure 5 10 PCI Express Link Layer x1 x4...

Page 27: ...terface Port Name I O Width Description Clock and Reset mpcs_rx_usr_clk_i In NL User interface Rx clock input mpcs_tx_usr_clk_i In NL User interface Tx clock input mpcs_tx_pcs_rstn_i In NL Active low...

Page 28: ...ignment enabling input port This function is useful if the automatic synchronization is not enabled The rising edge of this signal triggers the word alignment operation mpcs_get_lsync_o Out NL Link Sy...

Page 29: ...operation causes the PMA Tx driver to exit Electrical Idle condition 22 tx_pcs_clk cycles later mpcs_rxval_o Out NL PHY receive valid this signal is used to signal receive valid data It corresponds to...

Page 30: ...ow power state 2 b00 operational state epcs_txhiz_i In NL This signal is used to load Electrical Idle III in the Tx driver of the PMA macro epcs_rxidle_o Out NL This port is used to signal the Electri...

Page 31: ...IPE Interface PIPE interface is accessible when SerDes PCS is configured as PIPE mode PIPE mode is designed to work with PCI Express soft IP implemented by FPGA fabric Table 5 9 shows the detailed PIP...

Page 32: ...E16BIT is defined or not pipe_txdatak_i In 4 NL Transmit control character This signal is a per lane signal The width of this signal can be 1 bit 2 bits or 4 bits per lane depending on whether PIPE16B...

Page 33: ...w Frequency LF This signal is always set to 10 by the PHY for each lane pipe_local_get_preset_coef_i In NL Get local preset mapping to coefficient This signal is a per lane signal which is used by the...

Page 34: ...the activity detector circuit power down and move the PHY to either L1 1 Tx Common Mode voltage is still valid or L1 2 Tx Common Mode voltage is disabled pipe_txcommonmode_disable_i In NL L1 substate...

Page 35: ...le Electrical Idle detection pipe_tx_swing_LL_i In NL 2 5G 5G transmitter amplitude 1 b1 Reduced Swing 1 b0 Full Swing pipe_tx_margin_LL_i In 3 NL Transmitter test amplitude selection Used for test on...

Page 36: ...bit PHY_DATA_WIDTH pipe_rx_eq_eval_feedback_fom_LL_o Out 8 NL Refer to the pipe_linkevalfigure_o signal pipe_rx_eq_eval_feedback_dir_LL_o Out 6 NL Refer to the pipe_linkevalchange_o signal pipe_phy_st...

Page 37: ...x_data_LL_o pipe_rx_status_LL_o Out 3 NL PIPE Rx status 3 b000 Reserved 3 b001 SKP added 3 b010 SKP deleted 3 b011 Receiver detected 3 b100 Encoding error 3 b111 Disparity error 3 b101 Overflow error...

Page 38: ...c only for test purpose diffioclksel_i In 1 Dynamic clock source selection 1 b1 sd_ext_1_refclk_i 1 b0 sd_ext_0_refclk_i clksel_i In 2 Dynamic clock source selection 2 b11 sd_pll_refclk_i 2 b10 sd_ext...

Page 39: ...tial value the transmitter drives acjtag_highz_i In 1 When acjtag_mode_i 1 b1 assertion of this signal puts the PMA driver in high impedance acjtagpout_i In 1 ACJTAG Output Data acjtagnout_i In 1 ACJT...

Page 40: ...n bit 0 is the control signal for tx_data_64b 7 0 bit 1 is the control signal for tx_data_64b 15 8 bit 7 is the control signal for tx_data_64b 63 56 bit 1 0 of this signal can also be used as 2 bit bl...

Page 41: ...overflow Rx Path mpcs_rx_ch_dout_o 39 0 epcs_rxdata_o 39 0 rx_data 39 0 4 byte input data bit 39 30 byte_3 bit 39 rundisp bit or data bit 9 when being used in 10b mode bit 38 control character when b...

Page 42: ...ata bus rx_data_64b bit 0 corresponds to 4 byte idles which are carried by bit 31 0 of data bus rx_data_64b mpcs_rx_ch_dout_o 75 74 epcs_rxdata_o 75 74 rx_fifo_del 1 0 The indication of deletion for c...

Page 43: ...atus bit 3 FIFO overflow bit 2 FIFO underflow bit 1 FIFO is almost full bit 0 FIFO is almost empty Receive Status Signals rx_data_8b 39 29 19 9 The rundisp bit Shows the running disparity status rx_da...

Page 44: ...1 0 The indication of insertion for clock frequency difference compensation bit 1 corresponds to 4 byte idles which are carried by bit 63 32 of data bus rx_data_64b bit 0 corresponds to 4 byte idles...

Page 45: ...B Mode MPCS 64B 66B Mode Figure 5 13 shows the detailed channel block diagram in PMCS 64B 66B mode In this mode only 64B 66B PCS channel is expanded 8B 10B PCS channel and PMA Only channel are hidden...

Page 46: ...tor FPGA TN 02245 0 81 All rights reserved CONFIDENTIAL PMA Control Cal ibration FSM Equalization FSM PRBS Gen Chk PCI Express PCS Channel Quad Common Clock Reset Generation and BIST Gen Chk 64B 66B P...

Page 47: ...Mode levels Tx PLL M F N CDR PLL M F N Serializer Deserializer Transmitter Receiver AD Amplitude Pre Post Cursor Settings Tx Data 5 8 10 16 20 bits Tx CLK REF CLK Rx CLK Rx Data 5 8 10 16 20 bits Equ...

Page 48: ...ards specifications Take PCI Express as example the AC coupling capacitors should be placed near Tx side Figure 6 2 Figure 6 2 PCI Express AC Coupling Capacitors Location PLL Clock Setting Tx and Rx r...

Page 49: ...ity Invert modules between PMA and Tx Rx Gear Box are implemented to invert the data polarity for Tx Rx path if necessary PMA PMA Control Logic Calibration FSM Equalization FSM Register Space Rx Gear...

Page 50: ...F PMA PMA Controller Figure 6 4 PCI Express PCS PMA Controller Block Diagram MPCS 8B 10B PCS Figure 6 5 shows the block diagram of the 8B 10B PCS inside MPCS channel This block implements the most com...

Page 51: ...ide MPCS are only in 1 byte 2 byte mode There is 2 1 gearing logic in MPCS Tx path to convert 4 byte data flowing from fabric to 2 byte data for MPCS internal processing Similarly a 1 2 gearing exists...

Page 52: ...trl_3 data_3 8 rx_data 37 data_3 7 data_3 7 rx_data 36 data_3 6 data_3 6 rx_data 35 data_3 5 data_3 5 rx_data 34 data_3 4 data_3 4 rx_data 33 data_3 3 data_3 3 rx_data 32 data_3 2 data_3 2 rx_data 31...

Page 53: ...so that user logic can correctly sample them 6 4 1 3 Tx Channel Data Transfer Signals of Fabric MPCS Tx channel interface fall into two categories Signals tx_frcdisp tx_dispval and tx_frcdata are stri...

Page 54: ...latency is introduced by this FIFO Must use this mode if low latency or deterministic latency are required Lane to lane skew Extra lane to lane skew between every two bonded channels may be introduce...

Page 55: ...g the running disparity rules specified The functionality of this encoder is compatible with most 8B 10B PCS based protocols The 8B 10B encoder implements two modes 1 byte mode and 2 byte mode In 1 by...

Page 56: ...encoding the input data after the next data However the data stream seems to be separated into two streams encoded independently and then merged to one steam again Finally the encoded data are transm...

Page 57: ...search for word alignment pattern in the input parallel data then move the matched pattern to byte boundary and align the output data to the boundary The alignment operation is performed when walign_...

Page 58: ...ccessfully in SYNC state The Auto Aligner module locks the current boundary and avoids re alignment In SYNC state the FSM monitors continuously if there is any bad code appearing The bad_counter is ad...

Page 59: ...important to note that the mask code can be applied to both primary and secondary alignment patterns The corresponding pattern bit is applied to the pattern matching process when the related bit valu...

Page 60: ...g pattern matching Primary and secondary synchronization code are provided separately and the secondary synchronization code can optionally be disabled The Link Synchronization FSM supports both 10 bi...

Page 61: ...frequency adjustment between the recovered receive clock domain and the local system clock domain The Elastic Buffer performs clock compensation by inserting or deleting bytes at the position where S...

Page 62: ...elow the low water line this module adds additional SKIP pattern from the incoming SKIP pattern it matches to prevent underflow The minimum number of SKIP patterns after deletion can be set as one two...

Page 63: ...dule is 10 byte clock cycles or 100 UI but you can reconfigure this value to a lower value as per protocols It is recommended to set the real max skew plus one or two considering that the extra skew i...

Page 64: ...Aligner BER Monitor Tx FIFO and Rx FIFO Rx Gear Box Block Aligner De Scrambler 64B 66B Decoder Tx FIFO 64B 66B Encoder Scrambler Tx Gear Box 16b data TX Path RX Path 64B 66B PCS BER Monitor PRBS Gene...

Page 65: ...IEEE802 3 10GBASE R PCS It is not intended for receiver tests and the PRBS Checker module is not expected to receive this square wave pattern When square wave pattern is selected the PRBS Generator se...

Page 66: ...to adapt Tx path clock frequency and phase difference between 64B 66B PCS channel and fabric It serves in following two application cases Case I with GPLL In this case GPLL is required to generate a 1...

Page 67: ...r the data out of Rx FIFO becomes discontinuous considering that the frequency of write clock and read clock is the same but the bandwidth between the write side and the read side is different The wri...

Page 68: ...ck lock FSM specified in Clause 49 of IEEE802 3 which shifts the incoming data stream and detects the block boundary The bit number of shifting can be checked via related status registers The block lo...

Page 69: ...bit Mode 1 a 20 bit 1 1 usr_dbus 19 0 T0 usr_dbus 19 0 Mode 1 b 2 1 usr_dbus 39 0 T0 usr_dbus 19 0 T1 usr_dbus 39 20 10 bit Mode 2 a 10 bit 1 1 usr_dbus 9 0 T0 usr_dbus 9 0 Mode 2 b 2 1 usr_dbus 19 0...

Page 70: ...ork independently not aligned Table 6 8 Channel Alignment within One Quad Mode Quad Lane0 Lane1 Lane2 Lane3 Mode 1 2 lane alignment Mode 2 2 lane alignment Mode 3 2 lane alignment 2 lane alignment Mod...

Page 71: ...receive buffer is unterminated input and must be DC coupled out of chip This SDQx_REFCLKP N receive buffer supports voltage signal input or current signal such as High Speed Current Steering Logic HC...

Page 72: ...tx_pcs_clk N A This parallel data clock is generated by PMA Tx macro and used by MPCS to drive Tx data bus The source of this clock is Tx PLL rx_pcs_clk N A This parallel data clock is generated by P...

Page 73: ...abled the source of this clock can be tx_pcs_clk that comes from the Tx path of the same channel or tx_lalign_clk which is the common clock within bonded channels rx_pcs_clka is used in single channel...

Page 74: ...selected by MPCS depending on application cases This clock can be the divided by two version of its source clock tx_usr_clk Input This clock is a node of fabric clock tree The data sent by user logic...

Page 75: ...not every tx_out_clk in channels is really used The source of this clock is selected by MPCS depending on application cases This clock can be the divided by two version of its source clock rx_out_clk...

Page 76: ...k 0 and rx_pcs_clk 0 can be connected to all four channels inside the Quad The tx_pcs_clk and rx_pcs_clk from channel 2 are connected to Quad Common module too but tx_pcs_clk 2 and rx_pcs_clk 2 can be...

Page 77: ...om channel_0 of this Quad This introduces a usage limitation that channel_0 must be included in the multiple channel link tx_lalign_clk_in N A This clock is shared by two adjacent Quads It can be used...

Page 78: ...UI 3 125 156 25 2 2 10 6250 3125 312 5 1 312 5 10 2 156 25 20 SGMII 1 25 125 8 1 10 10000 1250 125 1 125 10 1 125 10 1KBASE X 1 25 125 8 1 10 10000 1250 125 1 125 10 1 125 10 SLVS EC Grade 3 59 2 4 10...

Page 79: ...ncy or deterministic latency A synchronous DFF is used to capture the input data instead of Tx FIFO The tx_out_clk drives FPGA global clock tree and a leaf node of this clock tree is used to drive use...

Page 80: ...igner rx_pcs_clk RX Path RX FIFO 2 1 DFF DFF Clock Tree DFF Fabric DFF rx_pcs_clka rx_lalign_clk tx_pcs_clk tx_lalign_clk rx_pcs_clkb rx_out_clk rx_usr_clk Figure 7 10 Case II b Clock Structure Case I...

Page 81: ...FIFO Channel 0 TX Path Tx Lane to lane Deskew Fabric DFF 2 1 Clock Tree 8B 10B Encoder Tx PMA Tx FIFO Tx Lane to lane Dekew Fabric DFF 2 1 Quad Common Channel 1 TX Path tx_pcs_clk0 tx_lalign_clk tx_pc...

Page 82: ...d each channel internal clock rx_out_clk0 and rx_out_clk1 The rx_out_clk0 is used to drive FPGA global clock tree and a leaf node of this clock tree returning to MPCS is used as the read clock of Rx F...

Page 83: ...divided by two version or divided by four of tx_pcs_clk and rx_pcs_clk respectively A General PLL GPLL is recommended to be used in fabric to generate the 156 25 MHz clock to drive both Tx XGMII data...

Page 84: ...n for the Rx FIFO read timing diagram The Rx FIFO also works as CTC FIFO to implements the functionality of clock tolerance compensation Rx Gear Box Block Aligner De Scrambler 64B 66B Decoder Rx FIFO...

Page 85: ...h considerations below PMA data width is 16 bit or 20 bit Gearing must be 1 1 PMA data width is 8 bit or 10 bit Gearing can be 1 1 or 2 1 PMA data width is 5 bit Gearing can be 1 1 2 1 or 4 1 These PM...

Page 86: ...but register access bus is working After mpcs_resetn_i is released by user logic SerDes PCS module checks whether or not all the following conditions are satisfied Then SerDes PCS module can decide i...

Page 87: ...e MPCS mode but several signal names are different Refer to Figure 7 20 and Figure 7 21 for detailed timing diagrams Valid Clock Valid Clock A B C D E F Valid Data Valid Clock Power Up lmmi_clk_i mpcs...

Page 88: ...Reset Sequence Rx Path Valid Clock Valid Clock A B C D E F Valid Data Valid Clock Power Up lmmi_clk_i epcs_clkin_i lmmi_resetn_i epcs_rstn_i epcs_txclk_o epcs_ready_o epcs_txval_i epcs_tx_pcs_rstn_i...

Page 89: ...ue of the signal because the high frequency component of the repeating value signal is less than the continuous flip signal This problem of previous bits affecting subsequent bits is referred to as In...

Page 90: ...e Signal after Receiver Equalization Figure 8 3 Typical Backplane Application with Rx Equalizer CertusPro NX device implements both Tx equalizer and Rx equalizer for multiple protocols supporting Tx e...

Page 91: ...B de emphasis post cursor ratio C 1 should be set as 0 167 and pre cursor ratio C 1 should be set as 0 000 The pre cursor ratio C 1 and post cursor ratio C 1 can be configured via PMA registers reg0a...

Page 92: ...programmable voltage value and a decision selection circuit that has the effect of varying the sample threshold voltage based on the sampled data stream The CTLE and DFE can be tuned to compensate for...

Page 93: ...PMA Loopback Figure 9 1 shows the two loopback modes implemented by PMA and PMA Controller PMA Near End Serial Loopback Mode and PMA Far End Parallel Loopback Mode In the near end serial loopback mod...

Page 94: ...e Tx FIFO What should be noted is that the Tx and Rx path clock must have no frequency difference In other words the Tx path and Rx path should share the same reference clock source This loopback mode...

Page 95: ...when MPCS works as 64B 66B PCS mode Rx Gear Box Block Aligner De Scrambler 64B 66B Decoder Rx FIFO Tx FIFO 64B 66B Encoder Scrambler Tx Gear Box 16b data TX Path RX Path 64B 66B PCS PMA BER Monitor PR...

Page 96: ...ference clock through the Phase Frequency Detector PFD operation Sampling clock at the receiver is not aligned to the center of the data eye during this step Phase lock or lock with reference to input...

Page 97: ...configurable settings and allows you to change the settings in that environment Care must be taken on when making the changes The design software tools cannot check the correctness of the changes you...

Page 98: ...drives the request data lmmi_wr_rdn_i lmmi_offset_i and lmmi_wdata_i at the same time and starts sampling lmmi_ready_o on the positive edge clock The LMMI master holds the lmmi_request_i and the reque...

Page 99: ...hown with bit7 as the significant bit on the left Table 10 1 shows the abbreviations that are used to indicate what type of register access for each is supported Table 10 1 Access Type Definition Acce...

Page 100: ...uring PCIe detect state That is why the recommended capacitance range is so narrow Table 11 1 PCI Express Recommend AC Capacitance PCIe Generation Minimum Typical Maximum Gen1 75 nF 265 nF Gen2 75 nF...

Page 101: ...bric side of the PCS the current disparity state of the PCS transmitter is unknown This is where the cordisp bit signal comes into play If the cordisp bit signal is asserted for one clock cycle upon e...

Page 102: ...erial Gigabit Media Independent Interface SGMII designed by Cisco is to convey network data and port speed between a 10 100 1000 PHY and a MAC with significantly fewer signal pins than required for GM...

Page 103: ...7 O0D1D2D3C4C5C6C7 10 8 h4B D1 D2 D3 O0 C4 C5 C6 C7 T0C1C2C3C4C5C6C7 10 8 h87 C1 C2 C3 C4 C5 C6 C7 D0T1C2C3C4C5C6C7 10 8 h99 D0 C2 C3 C4 C5 C6 C7 D0D1T2C3C4C5C6C7 10 8 hAA D0 D1 C3 C4 C5 C6 C7 D0D1D2T...

Page 104: ...configured as specific link rate based on 8B 10B PCS VESA DisplayPort Specification requires external AC coupling The recommended Capacitance are shown in Table 11 7 All DisplayPort Main Link lanes ne...

Page 105: ...ion FIFO 1 16 20 Rx Interface FIFO 2 8 12 Tx Path 64B 66B PCS Tx Interface FIFO 1 4 9 EPCS div4 clock 64B66B Encoder 1 3 3 Scrambler 1 1 1 Tx Gear Box N A 23 34 Rx Path Block Aligner 1 1 1 Descrambler...

Page 106: ...of the board Cursory analysis suggests that a third very high frequency capacitor should help reduce noise But experimental data has not shown any jitter benefit in real applications Board layout arou...

Page 107: ...REFCLKP N need be used In PCI Express PIPE mode the reference clock source from per quad package pins SDQx_REFCLKP N is also recommended when the number of lane is not lager than four For applications...

Page 108: ...to pass back the spectrum through the Transmitter What should be noted is that the reference clock from RC needs to be used in PCI Express Endpoint applications based on CertusPro NX SerDes PCS when t...

Page 109: ...his has the consequence of changing the Common Mode voltage from that of normal operation and hence takes at least 100 s to settle to or recover form assuming up to 200 nF AC Coupling capacitor This m...

Page 110: ...4 are for multiple channel applications MPCS foundational IP provides some parameters default settings for specific protocols and implements necessary connections between two or more quads for multipl...

Page 111: ...COAXPRESS DP EDP QSGMII SGMII SLVS_EC PCIE PCIE PCS XAUI 1KBASEX Active if Bypass PCS Unchecked Bypass PCS Checked Unchecked Unchecked Override TX PCS Mode Checked Unchecked Unchecked Override RX PCS...

Page 112: ...itions is true Protocol SLVS_EC Protocol COAXPRESS Protocol DP Protocol EDP Protocol PCIE Protocol PCIE PCS Rate1 Gbps See Table 7 5 N A Available if one of these conditions is true Protocol SLVS_EC P...

Page 113: ...ED ENABLED Active if Mode Tx only or Mode Rx and Tx 8b10b Encoder ENABLED DISABLED ENABLED Active if Mode Tx only or Mode Rx and Tx RX MPCS Reset ENABLED DISABLED DISABLED Active if Mode Rx only or Mo...

Page 114: ...D Sync Pattern Code 8B_CODE 10B_CODE 10B_CODE Active if Sync Pattern Alignment ENABLED Secondary Sync Pattern ENABLED DISABLED ENABLED Active if Sync Pattern Alignment ENABLED Primary Sync_det Pattern...

Page 115: ...the PCS instance Group Name Specifies the group name of the PCS instance Aligned channels have the same group name Mode Specifies the selected mode which can be Rx_only Tx_only or Rx_and_ Tx Data Rate...

Page 116: ...alignment pattern to 9 0 of the data bus or not For more details refer to register field align_2byte_dis in Table A 37 Use sync_det FSM Specifies whether to use sync_det FSM to control the automatic w...

Page 117: ...NX SerDes PCS primitive and MPCS foundational IP Table 14 4 Pin to Pin Connection Primitive Ports MPCS Foundational IP Port MPCS EPCS MPCS Foundational IP Port PIPE CH 3 0 _PMACLKIN mpcs_clkin_i epcs_...

Page 118: ...PE_POWER_DOWN mpcs_pwrdn_i epcs_pwrdn_i pipe_powerdown_i CH 3 0 _PIPE_RATE mpcs_rate_i epcs_rate_i pipe_rate_i CH 3 0 _PIPE_TXDETECTRX pipe_txdetectrx_i CH 3 0 _PIPE_RX_EQEVAL pipe_rxeqeval_i CH 3 0 _...

Page 119: ...mpcs_speed_o CH 3 0 _PIPE_RXEQ_FOM mpcs_fomrslt_o CH 3 0 _PIPE_PHY_STATUS mpcs_phyrdy_o pipe_phy_status_o CH 3 0 _PIPE_RX_EI mpcs_rxidle_o pipe_rx_elec_idle_o CH 3 0 _PIPE_RX_CLKREQ mpcs_ready_o pipe_...

Page 120: ...3 0 _PIPE_PHY_STATUS_LL pipe_phy_status_LL_o CH 3 0 _PIPE_RX_POLARITY_LL pipe_rx_polarity_LL_i CH 3 0 _PIPE_RX_ELEC_IDLE_LL pipe_rx_elec_idle_LL_o CH 3 0 _PIPE_RX_CLKREQ_N_LL pipe_rx_clkreq_n_LL_o CH...

Page 121: ...rx_data_enable_LL_o CH 3 0 _PIPE_RX_DATA_VALID_LL pipe_rx_data_valid_LL_o CH 3 0 _PIPE_RX_START_BLOCK_LL pipe_rx_start_block_LL_o CH 3 0 _PIPE_RX_SYNC_HEADER_LL pipe_rx_sync_header_LL_o CH 3 0 _PIPE_B...

Page 122: ...8 d25 reg18 RW Tx Amplitude ratio 8 d33 reg21 RW CDR PLL frequency comparator maximum difference 8 d34 reg22 RW CDR PLL frequency comparator counter 8 d35 reg23 RW EI4 mode register 8 d48 reg30 RO PM...

Page 123: ...ion 7 0 errcnt_dec RW 8 8 h20 In PCS driven mode the PMA control logic counts the number of errors detected by the PCS logic in order to decide how to switch back to frequency lock mode of CDR PLL Thi...

Page 124: ...Table A 7 Tx PLL M N Settings reg05 Field Name Access Width Reset Description 7 cnt250ns_max RSVD 1 1 b0 Internal usage 6 5 TxM RW 2 2 b10 Defines the Tx PLL M setting 2 b11 8 2 b10 4 2 b01 2 2 b00 1...

Page 125: ...ims to generate an internal timing event every 250ns or more internally for PMA Controller to calibrate CDR PLL lock to reference clock and data receive detect operation For example for PCIe Gen1 Gen2...

Page 126: ...NO_FCMP RW 1 1 b0 Disables the frequency comparator logic of the PCS driven CDR PLL control logic 1 b1 the frequency comparator logic is not any part of the condition for going from fine grain lock s...

Page 127: ...able A 17 CDR PLL Frequency Comparator Counter reg22 Field Name Access Width Reset Description 7 0 cdrpll_cnt_max RW 8 8 h4 This register defines the number of 256 clock cycles for evaluating the freq...

Page 128: ...t Error Sampler calibration has reached a minimum or maximum value 1 b1 reached 1 b0 not yet reached 0 arxt_err RO 1 NA Defines Rx Offset T calibration has reached a minimum or maximum value 1 b1 reac...

Page 129: ...ts down the Rx de serializer circuitry and RxClk while still maintaining CDR PLLs in lock for intermediate power savings 1 b0 normal operation 6 txhf_clkdn RW 1 1 b0 Tx PLL VCO control 1 b1 disables C...

Page 130: ...ta on the transmitted data 1 b0 normal operation 4 eff_lpbk RW 1 1 b0 Far end loopback control 1 b1 activates the far end loopback through PCIe elastic buffer fifo assuming 0ppm between recovered cloc...

Page 131: ...state machine to coarse grain mode In this state the CDR PLL performs a coarse grain lock on received data enabling to adjust its clock up to 5000 ppm 1 b1 forces the CDR PLL state machine to coarse g...

Page 132: ...Secondary Word Alignment Pattern Byte 0 8 h35 reg35 RW Secondary Word Alignment Patter Byte 1 8 h36 reg36 RW Secondary Word Alignment Pattern MSB 8 h37 reg37 RW Word Alignment Pattern Mask Code Byte...

Page 133: ...5 RW Primary SKIP Pattern Byte 1 8 h66 reg66 RW Primary SKIP Pattern Byte 2 8 h67 reg67 RW Primary SKIP Pattern Byte 3 8 h68 reg68 RW Primary SKIP Pattern Byte MSB 8 h69 reg69 RW Secondary SKIP Patter...

Page 134: ...d BIST Constant 1 Byte_1 8 he5 rege5 RW User Defined BIST Constant 1 MSByte 8 he6 rege6 RW User Defined BIST Constant 2 Byte_0 8 he7 rege7 RW User Defined BIST Constant 2 Byte_1 8 he8 rege8 RW User De...

Page 135: ...b_dis RW 1 1 b0 8B 10B Encoding Enable Specifies the 8B 10B encoding is enabled or disabled 1 b1 Encoding disabled 1 b0 Encoding enabled 3 tx_fifo_dis RW 1 1 b0 Tx FIFO Enable Specifies the Tx phase c...

Page 136: ...W 1 1 b0 8B 10B Decoding Enable Specifies the 8B 10B decoding is enabled or disabled 1 b1 decoding disabled 1 b0 decoding enabled 3 rx_fifo_dis RW 1 1 b0 Rx FIFO Enable Specifies the Rx phase compensa...

Page 137: ...he data bus 1 b0 in a 2 byte internal data bus width mode always put the LSByte of the word alignment pattern to 9 0 of the data bus 3 sec_waptn_dis RW 1 1 b0 Pattern Matching Enable Specifies whether...

Page 138: ...ifies the 20 bit secondary word alignment pattern In 10 bit width mode only bits 9 to 0 are applied Table A 43 Secondary Word Alignment Pattern MSB reg36 Field Name Access Width Reset Description 7 4...

Page 139: ...FSM Configuration 0 reg3a Field Name Access Width Reset Description 7 0 num_cal_sync RW 8 8 d3 Specifies the number of valid synchronization code groups or ordered sets that sync_det FSM must receive...

Page 140: ...oup 5 b10011 19 bits are slipped 19 is the maximum bit number 5 b00010 2 bits are slipped 5 b00001 1 bit is slipped 5 b00000 there is no bit slipped Table A 52 Primary Sync_Det Pattern Byte 0 reg3f Fi...

Page 141: ...ster reflects the bits 9 to 8 of secondary Sync_Det pattern byte 3 to 0 5 4 sec_sdptn_byte2 9 8 RW 2 2 h0 3 2 sec_sdptn_byte1 9 8 RW 2 2 h0 1 0 sec_sdptn_byte0 9 8 RW 2 2 h1 Table A 62 Sync_Det Patter...

Page 142: ...bled Table A 68 Maximum Lane to lane Skew reg51 Field Name Access Width Reset Description 7 4 reserved RSVD 6 3 0 max_lskew RW 4 4 h0 Maximum Lane to lane skew specified in byte If the number of lane...

Page 143: ...Secondary Lane Alignment Pattern Byte 1 Table A 76 Secondary Lane Alignment Pattern Byte 2 reg59 Field Name Access Width Reset Description 7 0 sec_laptn_byte2 RW 8 8 h0 Secondary Lane Alignment Patter...

Page 144: ...nd clk_comp_en are listed below ctc_fifo_en clk_comp_en 2 b0x bypass the input date of this module 2 b10 the module works as asynchronous FIFO without clock frequency compensation 2 b11 the module per...

Page 145: ...yte 3 reg67 Field Name Access Width Reset Description 7 0 pri_skip_byte3 7 0 RW 8 8 h0 Primary SKIP Pattern Byte 3 Table A 88 Primary SKIP Pattern MSB reg68 Field Name Access Width Reset Description 7...

Page 146: ...D 6 1 end_64b66b_dis RW 1 1 b0 Enable 64B 66B Encoder Specifies the 64B 66B Encoder is enabled or disabled 1 b1 64B 66B Encoder is disabled 1 b0 64B 66B Encoder is enabled 0 src_64b66b_dis RW 1 1 b0 E...

Page 147: ...the 64B 66B Descrambler is enabled or disabled 1 b1 64B 66B Descrambler is disabled 1 b0 64B 66B Descrambler is enabled Table A 99 64B 66B PCS CTC High Water Line Control reg84 Field Name Access Width...

Page 148: ...Width Reset Description 7 0 prtp_seed_a 15 8 RW 8 8 h0 This register defines byte 1 of 10GBASE R PCS test pattern seed A Table A 106 10GBASE R Test Pattern Seed A Byte 2 reg94 Field Name Access Width...

Page 149: ...RW 8 8 h0 This register defines byte 2 of 10GBASE R PCS test pattern seed B Table A 115 10GBASE R Test Pattern Seed B Byte 3 reg9d Field Name Access Width Reset Description 7 0 prtp_seed_b 31 24 RW 8...

Page 150: ...led 1 b1 transmit test pattern is enabled 1 b0 transmit test pattern is disabled 1 tx_prtp_test_sel RW 1 1 b0 Tx test pattern Selector Specifies the selected test pattern on the Tx path 1 b1 square wa...

Page 151: ...the number of errors received during a pattern test These bits are reset to all zeros when the test pattern error counter is read or upon execution of the PCS reset These bits are held at all ones in...

Page 152: ...t enable loopback A Table A 127 MPCS BIST Control 0 rege1 Field Name Access Width Reset Description 7 5 bist_ptn_sel RW 3 3 h0 BIST Pattern Selection Specifies the selected BIST Pattern 3 b111 Alterna...

Page 153: ...cifies the selected BIST sync header counter selection 2 b11 24 2 b10 14 2 b01 8 2 b00 5 Table A 129 User Defined BIST Constant 1 Byte_0 rege3 Field Name Access Width Reset Description 7 0 udbc 17 10...

Page 154: ...User defined BIST Constant value pattern 1 1 0 udbc 9 8 RW 2 2 h0 User defined BIST Constant 1 Byte_0 register reflects the lower 8 bits of the 10b User defined BIST Constant value pattern 1 Table A...

Page 155: ...000 01110 011100 1011 011100 0100 D15 0 0F 000 01111 010111 0100 101000 1011 D16 0 10 000 10000 011011 0100 100100 1011 D17 0 11 000 10001 100011 1011 100011 0100 D18 0 12 000 10010 010011 1011 01001...

Page 156: ...010001 1001 D30 1 3E 001 11110 011110 1001 100001 1001 D31 1 3F 001 11111 101011 1001 010100 1001 D0 2 40 010 00000 100111 0101 011000 0101 D1 2 41 010 00001 011101 0101 100010 0101 D2 2 42 010 00010...

Page 157: ...00 0011 D14 3 6E 011 01110 011100 1100 011100 0011 D15 3 6F 011 01111 010111 0011 101000 1100 D16 3 70 011 10000 011011 0011 100100 1100 D17 3 71 011 10001 100011 1100 100011 0011 D18 3 72 011 10010 0...

Page 158: ...010001 1101 D30 4 9E 100 11110 011110 0010 100001 1101 D31 4 9F 100 11111 101011 0010 010100 1101 D0 5 A0 101 00000 100111 1010 011000 1010 D1 5 A1 101 00001 011101 1010 100010 1010 D2 5 A2 101 00010...

Page 159: ...00 0110 D14 6 CE 110 01110 011100 0110 011100 0110 D15 6 CF 110 01111 010111 0110 101000 0110 D16 6 D0 110 10000 011011 0110 100100 0110 D17 6 D1 110 10001 100011 0110 100011 0110 D18 6 D2 110 10010 0...

Page 160: ...F8 111 11000 110011 0001 001100 1110 D25 7 F9 111 11001 100110 1110 100110 0001 D26 7 FA 111 11010 010110 1110 010110 0001 D27 7 FB 111 11011 110110 0001 001001 1110 D28 7 FC 111 11100 001110 1110 001...

Page 161: ...74 25 PMA Only 74 25 8 2 8 9504 1188 148 5 PMA Only 79 2 8 3 5 9504 1188 237 6 118 8 8 1 10 9504 1188 118 8 148 5 8 1 8 9504 1188 148 5 PMA Only 1 2288 76 8 8 1 16 9830 4 1228 8 76 8 PMA Only 76 8 8...

Page 162: ...04 2376 148 5 PMA Only 74 25 4 4 8 9504 2376 297 PMA Only 79 2 4 3 10 9504 2376 237 6 79 2 4 6 5 9504 2376 475 2 95 041 4 5 5 9504 2376 475 2 99 4 3 8 9504 2376 297 PMA Only 118 8 4 1 20 9504 2376 118...

Page 163: ...8 5 2 1 20 5940 2970 148 5 148 5 2 2 10 5940 2970 297 3 75 2 4 10 6000 3000 300 75 2 2 20 6000 3000 150 93 75 2 2 16 600 300 187 5 PMA Only 93 75 2 4 8 600 300 375 PMA Only 100 2 3 10 6000 3000 300 12...

Page 164: ...4608 230 4 144 2 2 16 9216 4608 288 PMA Only 153 6 2 3 10 9216 4608 460 8 4 752 79 2 2 3 20 9504 4752 237 6 79 2 2 6 10 9504 4752 475 2 95 041 2 5 10 9504 4752 475 2 99 2 3 16 9504 4752 297 PMA Only 1...

Page 165: ...2 5 78 125 1 5 16 6250 6250 390 625 PMA Only 97 656251 1 4 16 6250 6250 390 625 PMA Only 104 166 1 3 20 6250 6250 312 5 130 20831 1 3 16 6250 6250 390 625 PMA Only 156 25 1 2 20 6250 6250 312 5 6 375...

Page 166: ...1 135 8B 10B 8B 10B PCS 1000BASE X GigE 1 25 83 333 125 8B 10B 8B 10B PCS SGMII 1 25 83 333 125 8B 10B 8B 10B PCS XAUI 3 125 78 125 104 166 156 25 8B 10B 8B 10B PCS QSGMII 5 83 333 100 125 8B 10B 8B 1...

Page 167: ...CertusPro NX SerDes PCS Usage Guide Preliminary Technical Note FPGA TN 02245 0 81 2020 2021 Lattice Semiconductor 167 All rights reserved CONFIDENTIAL Appendix D Using Reveal SerDes Debug Tool TBD...

Page 168: ...commendations for Lattice SERDES FPGA TN 02077 ECP5 and ECP5 5G Family Data Sheet FPGA DS 02012 LatticeECP3 Family Handbook HB1009 LatticeECP3 Family Data Sheet FPGA DS 02074 LatticeECP3 SERDES PCS Us...

Page 169: ...age Guide Preliminary Technical Note FPGA TN 02245 0 81 2020 2021 Lattice Semiconductor 169 All rights reserved CONFIDENTIAL Technical Support Assistance Submit a technical support case through www la...

Page 170: ...Note 170 2020 2021 Lattice Semiconductor FPGA TN 02245 0 81 All rights reserved CONFIDENTIAL Revision History Revision 0 81 May 2021 Section Change Summary All Initial preliminary release Revision 0 7...

Page 171: ...www latticesemi com...

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