CertusPro-NX SerDes/PCS Usage Guide
Preliminary
Technical Note
FPGA-TN-02245-0.81
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63
All rights reserved. CONFIDENTIAL
Usually the write clock is from Rx PMA of each channel, while the read clock is from the Quad Common module. Check
the
s
ection for more details about the common clock.
The internal data bus width can be set as 1-byte or 2-byte mode. The input data of this module can be from 8B/10B
Decoder or from Word Aligner (8B/10B Decoder bypass mode). Both primary lane alignment pattern and secondary
lane alignment pattern are up to 4-byte length, the secondary one is optional and can be disabled. If the secondary
lane alignment pattern is enabled, the input data can match either primary or secondary pattern.
The alignment pattern length can be defined as 1, 2, or 4 bytes. If the length is 1, only byte 0 of lane alignment pattern
(primary and secondary) are used; if the length is 2, both byte 0 and byte 1 are used; if the length is 4, all four bytes of
alignment pattern are used.
A 4-bit mask code is provided to allow partially matching the alignment pattern (
). Each bit of the mask code
corresponds to one byte of the alignment pattern, value 1 means the corresponding byte is masked. Alignment pattern
byte being masked is ignored during matching. The mask code is applicable for both primary and secondary alignment
patterns.
Byte 0
Byte 1
Byte 2
Byte 3
bit[1]
bit[0]
bit[3]
bit[2]
Mask Code
Alignment Pattern
Figure 6.22. Lane Alignment Pattern Mask Code
The maximum lane-to-lane skew can be handled by this module is 10 byte clock cycles (or 100 UI), but you can
reconfigure this value to a lower value as per protocols. It is recommended to set the real max skew plus one or two,
considering that the extra skew is introduced by Quad-to-Quad handshaking (one for 1-byte mode, two for 2-byte
mode).
In 2-byte internal data bus width mode, this module shifts the coming data by one byte towards LSByte of the data bus
so that the first byte of the alignment pattern always appears at byte_0 (LSByte) of the data bus. When a data group
that matches the alignment pattern is found in the coming data, the first byte of the matching pattern can occur at
byte_0 or byte_1 of a 2-byte data bus. This introduces extra lane-to-lane skew. During performing lane alignment
operation, this module can move the data to 2-byte boundary to remove this skew.
shows how the data is
shifted. {A0, A1, A2, A3} is the 4-byte alignment pattern, and A0 is the first byte.
A0
D2
A2
A1
D1
D0
D3
A3
Padding
D2
A1
A0
D1
D0
A3
A2
bit[9:0]
bit[19:10]
bit[9:0]
bit[19:10]
Data before s hifting
Data after shifting
Figure 6.23. Data Shifting for Alignment
The lane alignment operation is triggered by the rising edge of signal rx_deskew_en. The rx_deskew_en should keep
asserted until next time the lane alignment operation is required. The module signals the achievement of lane
alignment by driving rx_get_lalign high as long as rx_deskew_en is asserted. The rx_get_lalign signal is driven low once
the de-assertion of rx_deskew_en signal is detected. Toggling rx_deskew_en (driven low and then high) can trigger
another session of lane alignment.
The rx_deskew_en signal can be driven low once the rising edge of rx_get_lalign is detected. Another choice is to keep
the rx_deskew_en high until the next lane alignment is required.
