Lattice Semiconductor CertusPro-NX, Usage Manual

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CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 59
All rights reserved. CONFIDENTIAL
This Link Synchronization FSM can optionally be enabled or disabled. If disabled, user logic should implement the state
machine to meet some criteria of synchronization or loss of synchronization and drive walign_en to request the
re-alignment operation once loss of synchronization is detected.
The maximum allowed alignment pattern length is 20-bit. You can define the length as either 10-bit or 20-bit. 8-bit and
16-bit patterns are implemented by applying mask code to 10-bit and 20-bit pattern respectively. Word aligner module
provides programmable primary alignment pattern. The total length of the alignment pattern register is 20-bit. Only
bit[9:0] are to be used when 10-bit pattern is used.
To support certain protocols or other user-defined protocols, Word Aligner module also provides programmable
secondary alignment pattern. The length of the alignment pattern is 20-bit, and bit[9:0] are used for 10-bit length
pattern. This secondary alignment pattern can optionally be enabled. If the secondary alignment pattern is enabled,
matching either primary or secondary pattern is allowed during detecting alignment pattern.
The programmable alignment pattern mask code is 20-bit length, which has one-to-one bitwise correspondence to the
20-bit alignment pattern. It is important to note that the mask code can be applied to both primary and secondary
alignment patterns. The corresponding pattern bit is applied to the pattern matching process when the related bit
value is set to 0. The corresponding pattern bit is ignored in the pattern matching process when the related bit value is
set to 1.
The internal data bus width can be configured as 1-byte mode or 2-byte mode. In 2-byte mode, the module can
optionally move the matched data bytes to the 2-byte boundary.
Some protocol always has the special symbol to be aligned on an even-numbered code-group boundary. The two-byte
alignment pattern defined in this example is “align pattern byte0” (LSByte) and “align patter byte1” (MSByte). The data
bus before 2-byte boundary alignment is shown in
Figure 6.13 .
Figure 6.13. Before 2-byte Boundary Alignment
After 2-byte boundary alignment, the LSByte of alignment pattern always appears at bit[9:0] of the 20-bit data bus, as
shown in
Figure 6.14 .
Figure 6.14. After 2-byte Boundary Alignment
Word aligner module can report the number of bits slipped during alignment operations. This feature helps in
calculating the latency through the receiver data path. The waveform in
Figure 6.15 and Figure 6.16 show how the
word aligner locates the data boundary in the input parallel data and align outputted data to the boundary. In this
example, the alignment pattern is defined as K28.5=0101111100.
XXXX XXXX
XXXX XXXX XXXX XXXX
XXXX XXXX Align Pattern Byte 0
Align Pattern Byte 1
Clock
bit[19:10]
bit[9:0]
XXXX XXXX
XXXX XXXX XXXX XXXX
XXXX XXXX Align Pattern Byte 1
Align Pattern Byte 0
Clock
bit[19:10]
bit[9:0]