CertusPro-NX SerDes/PCS Usage Guide
Preliminary
Technical Note
106
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FPGA-TN-02245-0.81
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Other Design Considerations
Simulation of the SerDes/PCS
All SerDes/PCS simulation models are located in the installation directory, under ….\cae_library\simulation\blackbox
directory.
PMA PLL Filter
To achieve a reasonable level of long-term jitter, it is vital to deliver an analog-grade power supply to the PLL. Typically,
an R-C or R-L-C filter is usually used, with the “C” being composed of multiple devices to achieve a wide spectrum of
noise absorption. Although the circuit is simple, there are specific board layout requirements for CertusPro-NX
SerDes/PCS.
The PLL filter should include series ferrite bead with Equivalent Series Resistance (ESR) approximately equal to
0.28 Ω. The ESR of the ferrite bead is critical. Too high ferrite bead ESR leads to a large IR drop. Too low ferrite
bead ESR leads to resonance in the board filter.
The series resistance of this filter is limited for DC reasons. Generally, it is recommended to see << 5% voltage drop
across this device under worst-case conditions.
The recommended ferrite bead is Murata Bead BLM15EG221SN1 [ESR = 0.28 Ω].
To achieve good low-frequency cut off, there should be a main ceramic capacitor (~47 µF) in the filter design.
Ceramic capacitors are preferred due to their lower parasitic resistance. As the filter also needs to sustain its
attenuation into moderately high frequencies, additionally, there is at least one low-ESL and low-ESR capacitor in
parallel (~470 nF for quad lane VCCPLLSDx). The routes from the high frequency capacitor(s) to the chip must be
kept short, and the capacitor must preferably be placed right underneath the chip on the reverse side of the board.
Cursory analysis suggests that a third, very high frequency, capacitor should help reduce noise. But experimental
data has not shown any jitter benefit in real applications.
Board layout around the high-frequency capacitor and the path from there to the pads is critical. It is vital that the
quiet ground and power are treated like analog signals.
The entire VCCPLLSDx and SDx_REFRET wiring path must not couple with any signal aggressors, especially any high
swing high slew rate signals such as TTL, CMOS, SSTL signals used in DDR busses. Trace shielding or line spacing
management is also required.
The SDx_REFRET pin serves as the local on-chip ground return path for VCCPLLSDx, so the external board ground
must not short with SDx_REFRET under any circumstance.
The power and ground traces should be short, and run close and parallel as far as possible, with large spacings to
adjacent traces. On no account should any connection be made from VCCPLLSDx or SDx_REFRET directly to board
power planes; only connect as described above, and depicted in
A high precision 976 Ω resistor (for 85 Ω differential impedance) is required to be used in 0402 or 0201 package for the
external reference resistor connected between SDx_REXT and SDx_REFRET. Better than or equal to 1% precision is
required.
shows the recommended external reference resistor for serval differential impedance
applications.
The power dissipation through this resistor is less than 1 mW during calibration. Dissipation is null, if calibrator
code is parked at all-zeroes.
The routes from the reference resistor to the chip must be kept short and the resistor must preferably be placed
right underneath the chip on the reverse side of the board.
Note that the capacitance of signal trace routes in FR4 is typically 4pF/inch. Each additional inch of trace increases
RC settling time constant by about 5 ns and hence add extra 20 ns for each step of the calibration process.
