7. Front Panel Interface
PLM+ SERIES Operation Manual rev 3.0.1
57
7.11.5.3. Breaker Emulation Limiter
MENU > FRAME > BEL CONF
The Breaker Emulation Limiter (BEL) provides Ampere selection (5-32 A) and breaker type selection
(CONSERVATIVE, FAST and UNIVERSAL). Select by pressing the adjacent button then use the rotary encoder to
change the parameter.
7.11.5.4. Network
MENU > FRAME > NETWORK
parameters (except Redundancy) are view-only on the front panel and are either not editable, or can only be
adjusted via the Lake Controller.
and whether the Lake Controller is online.
•
IP Addr: Displays the Internet Protocol address for the selected unit and can only be changed via the Lake
Controller software. Please refer to the Lake Controller Operation Manual for further details.
•
MAC: Displays the unique Media Access Control Ethernet address for the processor. This value cannot be
changed.
•
•
Primary and Secondary network connection status as well as Lake Controller connection status
•
Mask: Displays the IP address subnet mask for the selected unit and can only be changed via the Lake
Controller software. Please refer to the Lake Controller Operation Manual for further details.
•
ro Conf, Auto - DHCP or Fixed IP)
•
Redundancy: Displays the dual redundancy status for the Frame (ON/OFF) This mode can be changed by
een. Changing redundancy mode
requires a power cycle to activate.
7.11.5.5. Latency Match
To turn Latency Match on or off, select the parameter using the adjacent button then change the status using the
rotary encoder.
By default, PLM+ products exhibit the exact same input-to-output latency as the PLM and D Series products.
However, the PLM+, PLM and D Series products have a greater latency compared to the Lake processors of LM
Series. By enabling the Latency Match feature, the LM Series will add delay to match overall processing delay of
the PLM, PLM+, and D Series. This regards Analog and AES only. Dante is not part of Latency match.
Exception: Latency match will not function correctly when running 48k based AES input using the primary clock
domain.
The maximum RMS input current varies, and therefore a desired value is configured and the actual
value is displayed within brackets.
