COMe-bSL6 – User Guide Rev. 1.4
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Features and Interfaces
3.1.
LPC
The Low Pin Count (LPC) Interface signals are connected to the LPC Bus bridge located in the CPU or chipset. The LPC
low speed interface can be used for peripheral circuits such as an external Super I/O Controller that typically
combines legacy-device support into a single IC. The implementation of this subsystem complies with the COM
Express® Specification. The COM Express® Design Guide maintained by PICMG provides implementation information
or refer to the official PICMG documentation for more information.
The LPC bus does not support DMA (Direct Memory Access). When more than one device is used on LPC, a zero delay
clock buffer is required. This leads to limitations for ISA bus and SIO (standard I/O(s) like floppy or LPT interfaces)
implementations.
All Kontron COM Express® Computer-on-Modules imply BIOS support for the following external baseboard LPC Super
I/O controller features for the Winbond/Nuvoton 83627DHG-P.
Table 23: Supported BIOS Features
3.3V 83627DHG-P
AMI EFI APTIO V
PS/2
Not specified
COM1/COM2
Supported
LPT
Supported
HWM
Not supported
Floppy
Not supported
GPIO
Not supported
Features marked as not supported do not exclude OS support (e.g., HWM is accessible via SMB). If any other LPC
Super I/O additional BIOS implementations are necessary, contact Kontron Support.
3.2.
S
erial Peripheral Interface (SPI)
The Serial Peripheral Interface Bus (SPI bus) is a synchronous serial data link standard. Devices communicate in
master/slave mode, where the master device initiates the data frame. Multiple slave devices are allowed with
individual slave select (chip select) lines. SPI is sometimes called a four-wire serial bus, contrasting with three, two
and one-wire serial buses.
The SPI interface can only be used with a SPI flash device to boot from the external BIOS on
the baseboard.
3.2.1.
SPI boot
The COMe-bSL6 supports boot from a 16 MB 3V serial external SPI Flash. Pin A34 (BIOS_DIS0#) and pin B88
(BIOS_DIS1#) configure the SPI Flash as follows:
Table 24: SPI Boot Pin Configuration
Configuration BIOS_DIS0#
BIOS_DIS1#
Function
1
open
open
Boot on module BIOS
2
GND
open
Not supported
3
open
GND
Boot on baseboard SPI
4
GND
GND
Not supported
