COMe-bSL6 – User Guide Rev. 1.4
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// 56
Pin
COME Signal
Description
Type
Termination
Comment
B36
USB7-
USB 2.0 differential data pairs port 7
DP-I/O
PD 14.25 k
Ω
to
24.8 k
Ω
in PCH
B37
USB7+
B38
USB_4_5_OC#
USB overcurrent indicator port 4/5
I-3.3
PU 10 k
Ω
, 3.3 V (S5)
B39
USB5-
USB 2.0 differential data pairs port 5
DP-I/O
PD 14.25 k
Ω
to
24.8 k
Ω
in PCH
B40
USB5+
B41
GND
Power Ground
PWR GND
B42
USB3-
USB 2.0 differential data pairs port 3
DP-I/O
PD 14.25 k
Ω
to
24.8 k
Ω
in PCH
B43
USB3+
B44
USB_0_1_OC#
USB overcurrent indicator port 0/1
I-3.3
PU 10 k
Ω
, 3.3 V (S5)
B45
USB1-
USB 2.0 differential data pairs port 1
DP-I/O
PD 14.25 k
Ω
to
24.8 k
Ω
in PCH
B46
USB1+
B47
EXCD1_PERST#
Express Card expansion, reset port 1
O-3.3
PD 10 k
Ω
B48
EXCD1_CPPE#
Express Card expansion, capable card request
port 1
I-3.3
PU 10 k
Ω,
3.3 V
(S0)
B49
SYS_RESET#
Reset button input
I-3.3
PU 10 k
Ω,
3.3 V
(S5)
B50
CB_RESET#
Reset output from Module to Carrier Board
O-3.3
PU 10 k
Ω,
3.3 V
(S5)
B51
GND
Power Ground
PWR GND
B52
P
PCI Express receive lane 5
DP-I
B53
PCIE_RX5-
B54
GPO1
General Purpose Output 1
O-3.3
PD 100 k
Ω
B55
P
PCI Express receive lane 4
DP-I
B56
PCIE_RX4-
B57
GPO2
General Purpose Output 2
O-3.3
PD 100 k
Ω
B58
P
PCI Express receive lane 3
DP-I
B59
PCIE_RX3-
B60
GND
Power Ground
PWR
B61
P
PCI Express receive lane 2
DP-I
B62
PCIE_RX2-
B63
GPO3
General Purpose Output 3
O-3.3
PD 100 k
Ω
B64
P
PCI Express receive lane 1
DP-I
B65
PCIE_RX1-
B66
WAKE0#
PCI Express Wake Event wake up signal
I-3.3
PU 10 k
Ω
, 3.3 V (S5)
B67
WAKE1#
General purpose Wake Event wake up signal, to
implement wake-up on PS2 keyboard or mouse
I-3.3
PU 10 k
Ω
, 3.3 V (S5)
B68
P
PCI Express receive lane 0
DP-I
B69
PCIE_RX0-
B70
GND
Power Ground
PWR GND
B71
LVDS channel B data pair 0
DP-O
B72
LVDS_B0-
B73
LVDS channel B data pair 1
DP-O
B74
LVDS_B1-
B75
LVDS channel B data pair 2
DP-O
B76
LVDS_B2-
B77
LVDS channel B data pair 3
DP-O
B78
LVDS_B3-
B79
LVDS/BKLT_EN
LVDS or EDP panel backlight enable (ON)
0-3.3
PD 100 k
Ω
B80
GND
Power Ground
PWR GND
B81
LV
LVDS Channel B Clock
DP-O
20 MHz -80 MHz
B82
LVDS_B_CK-
B83
LVDS_BKLT_CTRL
LVDS or EDP panel backlight brightness control
O-3.3