Keysight M9502A, User Manual, Page: 91 / 142

Keysight M9502A/M9505A AXIe Chassis User Guide 81
Chassis Synchronization and Triggering Features and Functions
This
section of the
chassis
Web Interfac
e
is
used
to
enable
or
disable (by
setting to
high
impedance) the
Trigger
Bus
Outpu
t Buffers.
By
checking
a
c
heck
box,
a
“1
”
is
w
ritten
to
M950x T
rigger
Subsy
stem
(shown
for
the
M9505
A
AXIe
Chassis)
T
he factory
default
is that
all bi-directional
signals show
n
below
are three-stated
(high impedance) at
pow
er-on
.
By
checking
a
check
box,
a
1
is
w
ritten
to
the associated
bit
in
the
Trigger Bus Outp
ut
Enable Register, w
h
ich
enabl
es
the
associated buffer.
Clearing
the check
box
w
rites
a “0”
to the
register w
h
ich disables
that
p
articular buffer.
Slot 4 Slot 5
nal
nal
NOTE:
The
phrase “factory
defa
ult” means
“factory
defau
configuratio
n”. This
is
the
pow
er-o
n
configura
tio
n settings
are
shipped
w
ith
the
chassis
from
the
factory.
The
pow
er
-
p
Disabling a buffer
allow
s
that
trigger
signal to
be driven by
one
of the
slots.
As
show
n
on
the
diagram, the slot-driven signal
can
then
be used
as
an input
to the
Crosspoint
Slot 2 Slot 3
Bi-directio
Bi-direction
are
shipped
w
ith
the
chassis
from
the
factory.
The
pow
er
configuratio
n
settings can
be chang
e
d
from
the original
fa
default
configuratio
n
settings to
other
settings using
the
SaveAsDefa
ult() method, w
h
ich
saves
the
current
trigger
subsy
stem configura
tio
n
as
the new
default
configuratio
n
.
TRIG11
Sw
itch.
Trigger Bus Output
Enable Register
(factory
defa
ult conten
ts =
0,
all drivers
are
high-impeda
nc
e)
bit
8
G9
RIG10
TRIG11
Slot 1
SYNC
11
10
9
8
7
6
5
4
3
2
1
0
TRIG10
TRIG9
TRIG8
TRIG7
TRIG6
TRIG5
TRIG4
TRIG3
TRIG2
TRIG1
TRIG0
When
the chassis
is
next
pow
er
cy
cled, the just-saved (ag
via
SaveAsDefault)
pow
er-o
n def
ault configuration setting
be
applied,
not the pow
er-o
n
settings associated
w
ith
the
original factory
defa
ult
configura
tio
n.
0
bit
G1
RIG2
TRIG3
TRIG4
TRIG5
TRIG6
TRIG7
TRIG8
TRIG
TR
T
1
G2
TRIG3
STRIG4
STRIG5
11
10
9
8
7
6
5
4
3
2
1
0
1
.
Using
the
chassis Web Interfac
e
2
U
i
th
h
i
ft
f
t
l
(SFP)
Methods of configuring
the trigger
subs
y
s
te
m:
The trigger
subsy
stem can
be configure
d
us
ing any
of
the follow
ing five
methods:
TRIG0
Trigger Bus
TRIG
TR
T
STRIG1
STRI
ST
Star
Tri
gg
er
IG5
IG4
IG3
IG2
IG1
2
.
U
s
ing
th
e c
h
ass
is so
ft
fron
t pane
l
(SFP)
3
.
Programmatically
using
the AgM950
xSC
IVI-COM
driver
4
.
Programmatically
using
the AgM950
xSC
IVI-C
driver
5
.
Programmatically
using
the LabVI
EW driver
The virtual
sw
itch
p
ositions on
this
dia
g
ram are
show
n
TRIG0 TRIG1 TRIG2
Output Buffers
Star Trigger
Output
Enable Register
(factory
defa
ult
gg
Output
Buffers
STR
STR
STR
STR
STR
In
the
SFP
extract below
, the
TRIG1
outpu
t has
been
connect
e
d to
the
TRIG0
input, as
also
indicated by
the
connectin
g black
dot
at
right.
Because the
TRIG0
outp
ut isn’t
enable
d, this
indicates
that
TRIG0
is
originating
from
one
of
the
chassis
slots
The
fact
that
the
pg
being controlled by
their
res
pective
IVI-COM properties.
TRIG3 TRIG4 TRIG5 TRIG6
contents =
0,
all
drivers are
high
impedance)
TRIG0
is
originating
from
one
of
the
chassis
slots
.
The
fact
that
the
TRIG1
outp
ut is
enable
d indicates
that
TRIG1
is
driving
the
chassis
slots.
TRIG7 TRIG8 TRIG9
TRIG10 TRIG11
T
riggerOutEnable
T
riggerOutInvert
(factory
defa
ult
=
False)
Ti
O
tP
l
d
Crosspoint Sw
itch
STRIG1 STRIG2 STRIG3
1
.
An
input
(horizontal) signal
can
be
connect
e
d to
any
number of
outpu
t
(vertical
) si
g
nals.
Static
0
Static 1
T
riggerInInvert
(factory
defa
ult
=
False)
T
riggerOutEnable
(factory
defa
ult
=
Fa
False
T
ri
gger
O
u
tP
u
lse
d
(factory
defa
ult
=
False)
False
STRIG4 STRIG5
()
g
2
.
Each outpu
t
(vertical)
signal w
ill
alw
ay
s
be
connect
e
d
to one
input
(horizontal)
signal.
By
default,
each outp
ut
signal
is
connect
e
d
to
the Static
0
input .
False
Input level:
-5V to
+5V
Minimum voltage sw
ing: 250mV
Input
impedance:
4K
ohms
(pull
up
Static
0
(factory
defa
ult
=
False)
The comparator output is
non-
invertin
g
relative
Tr
u
e
80-160 ns
pulse genera
tor
on rising
edge
of
TRIGOUT
CP
True
SMA
Trigger Out
Inv
er
si
on Block
F
lag1
F
lag2
F
lag3
SMA
TRIGGER
IN
SM
TRIG
OU
Tr
u
e
False
SMA
Trigger
In
Input
impedance:
4K
ohms
(pull
-up
to 2.5V)
RUN
C
+ -
g
to the
input.
TRIGOUT
_
CP
80-160 ns
pulse
TRIGOUT
CP
F
lag3
F
lag4
Run property
(factory
defa
ult
=
False)
OU
SMA
Trigger
In
Inv
er
si
on Block
Output voltage
level:
3.3V
Output load:
50
ohms
MultiFrame
IN
FLAGS
MultiFrame
OUT
FLAGS
SY
NC_CP
TRIGOUT_CP
-
T
riggerInT
hreshold
--
Can be
set
in
3.2 mV
increments from
-5V
to
+5V
(factory
default
=
1
65V)
TRIGOUT
_
CP
FLAG1B, FLAG2B, FLAG3B, FLAG4B
SY
NC
False
(to slave
chassis)
Flag1
Flag2
Flag3
Flag4
CLK100
IN
FLAGS
OUT
FLAGS
SYNC to backplane
+5V
(factor
y
default
=
1
.65V)
D
Q
CLK100
True
False
FLAG1A, FLAG2A, FLAG3A, FLAG4A, SY
NC,
RUN
True
D
Q
SY
NC
ON
is
False
if
no
chassi
s
is
False
CLK100
(from master
chassis)
Flag
Router and
Run Router
ON
CLK100
Sy
ncT
hroughCrosspointS
w
itch
(factory
defa
ult
=
True)
RUN
,
ON
SMA
TRIGGER
IN
ON
is
False
if
no
chassi
s
is
connected
to the MULTIFRA
ME
INPUT connector