Juniper G10 CMTS, Hardware Manual

Page: 47 / 210

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Hardware Component Overview
DOCSIS Module
31
Functional Characteristics
The DOCSIS Module is fully compliant with CompactPCI Specification 2.0 R3.0 , Oct.1, 1999.
The module contains a 6 U (267 mm) x 340 mm card with an 8 HP (40 mm), double-wide
front panel. Physical dimension are provided in Table 8 on page 36. The module installs from
the front of the chassis and is hot-swappable.
Each DOCSIS Module has a companion HFC Connector Module or SIM on the back side of
the midplane (see Figure 8 on page 15). All network-side traffic and HFC-side traffic
transmitted and received by the DOCSIS Module passes through the midplane to and from
the HFC Connector Module or SIM. Thus, no external connections to the DOCSIS Module are
required from the front of the chassis for normal operation.
Downstream data flow comes to the DOCSIS Module from the HFC Connector Module or SIM
in the form of Internet data in IP packets. The module performs various processes described
in “Data Packet Processing” on page 32. The data is encapsulated first into DOCSIS frames,
then into an MPEG transport stream. The transport stream is modulated onto an RF signal for
downstream distribution to the cable modems.
The upstream data flow is contained in PDUs (protocol data units) of varying length
transmitted as TDMA bursts on specifically allocated frequencies. This process is controlled
by advanced timing algorithms.
The DOCSIS Module also has other innovations to achieve high levels of density and
performance. It combines the high-density Broadband Cable Processor ASIC with four
500 MHz MPC7410 processors for high-performance network edge processing in an
asymmetric multiprocessing architecture. The 60x system bus connecting the MPC7410
processors has a data rate of 8 Gbps. This module contains 384 MB of RAM, 128 KB of
NVRAM, and 1.5 MB of flash memory.
It runs DOCSIS MAC protocols, the scheduler, and all data path processing such as packet
filtering, rate-limiting, traffic shaping, and 802.1D bridging. The Broadband Cable Processor
ASIC provides hardware assist for the following functions: MAC protocol, scheduling,
concatenation, fragmentation, encryption and decryption, spectrum analysis, noise
cancellation, pre-equalization, and per-SID (Service Identifier) statistics.
The proprietary Broadband Cable Processor ASIC supports up to four downstream and eight
or 16 upstream interfaces (depending on the DOCSIS Module model). It enables the
implementation of QPSK and 16QAM modulation on upstream channels with very low
packet loss in the presence of noise. This allows tighter scheduling of packets, thereby
efficiently utilizing more of the RF spectrum. Downstream modulation uses 64QAM or
256QAM.
With up to eight DOCSIS Modules per chassis, the maximum interface capacity is
32 downstream interfaces and 128 upstream interfaces.
Figure 13 on page 32 shows a block diagram of the DOCSIS Module and Figure 14 on
page 33 shows the packet processing flow.