NT-2000 REF Manual
Theory of Operation
8-3
8. Summarized Theory of Operation
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3 /6
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8 . 7 . O p e r a ti n g
P r i n c i p l e o f NT– 2 0 0 0 / D E BE G 2 9 0 2
Figure 9-1 shows interconnections between the printed circuit boards (PCBs)
comprising the NT–2000/DEBEG 2902 system and interface connections from the PCBs
to data input/output ports and peripheral devices. Figure 9-2 is the schematic of the
antenna selector which allows selection of the desired antenna from a single keystroke
on the keypad.
To follow the circuit description below, see also the schematics of the receivers, CPU
PCB and power PCB attached.
Receiver Circuit
To receive the three NAVTEX frequencies (518 kHz, 490 kHz and 4209.5 kHz), the
system incorporates two independent receivers (first and second receivers) plus a
frequency converter. The 518 kHz international broadcast is picked up by the first
receiver (NT–2000A), and the 490 kHz national broadcast, by the second receiver
(NT–2000B). The second national broadcast frequency of 4209.5 kHz is first converted
down to 490 kHz by the frequency converter (N501–F/C–A) and then fed to the second
receiver.
Each receiver is of straight amplifier type, consisting of two stages (field–effect
transistors V6 and V7) of amplification, followed by an IC amplifier (U1) and an
amplitude limiter (diode pair V8 and V9). Located at the end of the amplification chain
is an FM detector that consists of crystal–controlled oscillator B1, its associated parts
and part of the IC circuitry), which demodulates a frequency–shifted (
±
85 Hz) RF
NAVTEX signal into a stream of baseband DC pulses at 100 baud using a quadrature
detection technique. The detected output is then fed to the CPU via opto–isolator K2.
To test whether each receiver is functioning properly, a NAVTEX signal generator is
provided on the PCB, consisting of quartz crystal B2, IC ( N1) and their associated parts.
When the self–diagnostic test function is activated via the menu, the CPU PCB supplies
a test signal (modulating signal) to the generator via opto–isolator K4 and transistor
switch V13, allowing the generator to produce a simulated frequency–shifted signal at
the receiver frequency, and feeds it to the receiver input through relay K1.
CPU Circuit
The CPU PCB (N501–CPU–C) is built around a 16–bit single–chip microcomputer
(U10) that has a CPU clocked at 24 MHz by crystal–controlled oscillator X1, and
on–chip flash ROM for program software and on–chip RAM providing memory space for
data processing of the demodulated signal. An external static RAM (SRAM) chip (U5,
512 kB) is mounted for message and ID storage, and is backed up by large capacity
capacitor C6 (1.0 farad) for approx. 10 days in the event of continuous power–off.
Another external SRAM (U1, 256 kB) is used to hold text for display on the LCD screen.
U3 and U4 are factory–programmed to jointly act as a display controller to perform
various display control functions and text scrolling. The input/output interface between
the CPU and externally connected devices consists of three external ports: U7 for the
RS–232C port, U12 for the
*
RS–422 port and an opto–isolator for the I/O DATA port.
*
Input lines to the RS–422 port are insulated from ground by opto–isolators (ISO2, ISO3).
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