IWILL BD100 Plus, User Manual

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4.5.10 8 Bit I/O Recovery Time
This field specifies the number of clocks, which the system will delay after the completion of an 8 bit
input/output request.
Options 1 (*) / 2 / 3 / 4 / 5 / 6 / 7 / NA / 8
4.5.11 16 Bit I/O Recovery Time
This field specifies the number of clocks, which the system will delay after the completion of an 16
bit input/output request.
Options 1 (*) / 2 / 3 / NA / 4
4.5.12 Memory Hole At 15M-16M
Some add-in cards need to re-map its resource to a block of main memory address range. Any host
cycles that match this memory hole are passed on to the add-in cards.
Options Enabled
Disabled (*)
4.5.13 Passive Release
When enabled, the south bridge PIIX4 will support the Passive Release mechanism when it is a PCI
master. The PCI revision 2.1 compliant requires this field to be enabled. This field is for experienced
users only.
Options Enabled (*)
Disabled
4.5.14 Delayed Transaction
When enabled, the south bridge PIIX4 will supports the Delayed Transaction mechanism when it is
the target of a PCI transaction. The PCI revision 2.1 compliant requires this field to be enabled. This
field is for experienced users only.
Options Enabled
Disabled (*)
4.5.15 AGP Aperture Size (MB)
This field specifies the size of system memory that can be used for AGP graphics aperture.
Options 4 / 8 / 16 / 32 / 64 (*) / 128 / 256
4.5.16 Set SDRAM Timing By SPD
When Enabled, the system BIOS will reference data of DIMM module EEPROM.
Options Enabled (*)
Disabled