REL1.0
Page 69 of 106
RZ/G1H Qseven Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Table 25: JTAG Header Pin Out
Pin
No
Pin Name
Signal Name
Signal Type /
Termination
Description
1
VCC
VCC_3V3
O, 3.3V Power VREF reference Voltage.
2
VCC
VCC_3V3
O, 3.3V Power
Supply Voltage.
3
JTAG_TRSTB
JTAG_TRSTB
I, 3.3V CMOS
JTAG test reset signal.
4
GND
GND
Power
Ground.
5
JTAG_TDI
JTAG_TDI
I, 3.3V CMOS
JTAG test data Input
.
6
GND
GND
Power
Ground.
7
JTAG_TMS
JTAG_TMS
I, 3.3V CMOS/
10K PU
JTAG test mode select.
8
GND
GND
Power
Ground.
9
JTAG_TCK
JTAG_TCK
I, 3.3V CMOS/
10K PD
JTAG test clock.
10
GND
GND
Power
Ground.
11
-
-
10K PD
-
12
GND
GND
Power
Ground.
13
JTAG_TDO
JTAG_TDO
O, 3.3V CMOS
JTAG test data Output.
14
GND
GND
Power
Ground.
15
RSTBN
RSTBN
I,3.3V CMOS/
10K PU
Reset Signal.
16
GND
GND
Power
Ground.
17
NC
NC
-
NC.
18
GND
GND
Power
Ground.
19
-
-
10K PD
-
20
GND
GND
Power
Ground.