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RZ/G1H Qseven Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6.2
PCIe Channel0 Port
The RZ/G1H Qseven carrier board supports one PCI Express Gen2.0 lane through RZ/G1H
CPU’s
PCIe interface. PCIe
reference clock from Qseven MXM connector is connected to two output clock buffer and then connected to PCIex4
connector and Mini PCIe connector for clock reference.
The PCIe channel0 signals of Qseven MXM connector is connected to 1:2 Multiplexer/Demultiplexer switch and then
one output of this Multiplexer/Demultiplexer switch is connected to PCIex4 connector and other one to Mini-PCIe
connector. The selection between PCIex4 connector and Mini-PCIe connector can be done by setting the 6
th
bit of
Board configuration switch (SW2) to appropriate position.
If the 6
th
bit of Board configuration switch is set to ON position, then PCIe channel0 of Qseven MXM connector is
connected to PCIex4 connector which is physically located at the top of the board as shown below.
Figure 9: PCIex4 Connector
