REL1.0
Page 24 of 106
RZ/G1H Qseven Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
Qseven MXM
Connector Pin
Name
Signal Name
Signal Type/
Termination
Description
109
eDP0_TX2-/
LVDS_A2-
DU_LVDS0_CH2_N
I, 1.8V LVDS
LVDS primary channel differential pair2
negative.
This pin is connected to LVDS Receiver.
110
eDP1_TX2-/
LVDS_B2-
DU_LVDS1_CH2_N
I, 1.8V LVDS
LVDS secondary channel differential pair2
negative.
This pin is connected to secondary LVDS
connector (J27) in carrier board.
111
LVDS_PPEN
GPIO_LVDS_PPEN(G
P5_28)
I, 3.3V CMOS/
10K PU
LCD Panel Power Enable.
112
LVDS_BLEN
GPIO_LVDS_BLEN(GP
3_11)
I, 3.3V CMOS/
10K PU
LCD Panel Backlight Enable Control.
113
e/
DU_LVDS0_CH3_P
I, 1.8V LVDS
LVDS primary channel differential pair3
positive.
This pin is connected to LVDS Receiver.
114
e/
DU_LVDS1_CH3_P
I, 1.8V LVDS
LVDS secondary channel differential pair3
positive.
This pin is connected to secondary LVDS
connector (J27) in carrier board.
115
eDP0_TX3-/
LVDS_A3-
DU_LVDS0_CH3_N
I, 1.8V LVDS
LVDS primary channel differential pair3
negative.
This pin is connected to LVDS Receiver.
116
eDP1_TX3-/
LVDS_B3-
DU_LVDS1_CH3_N
I, 1.8V LVDS
LVDS secondary channel differential pair3
negative. (Optional)
This pin is connected to secondary LVDS
connector (J27) in carrier board.
117
GND
GND
Power
Ground.
118
GND
GND
Power
Ground.
119
e/
LVD
DU_LVDS0_CLK_P
I, 1.8V LVDS
LVDS primary channel differential Clock
positive.
This pin is connected to LVDS Receiver.
120
e/
LVD
DU_LVDS1_CLK_P
I, 1.8V LVDS
LVDS secondary channel differential Clock
positive. (Optional)
This pin is connected to secondary LVDS
connector in carrier board.
121
eDP0_AUX-/
LVDS_A_CLK-
DU_LVDS0_CLK_N
I, 1.8V LVDS
LVDS primary channel differential Clock
negative.
This pin is connected to LVDS Receiver.
122
eDP1_AUX-/
LVDS_B_CLK-
DU_LVDS1_CLK_N
I, 1.8V LVDS
LVDS secondary channel differential Clock
negative. (Optional)
This pin is connected to secondary LVDS
connector (J27) in carrier board.