Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
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Datasheet Volume One
2.5.2.6.24
Accumulated Energy Status Read
This service can return the value of the total energy consumed by the entire processor
package or just the logic supplied by the VCC power plane as specified through the
parameter field in
Table 2-8
. This information is tracked by a 32-bit counter that wraps
around and continues counting on reaching its limit. Energy units for this read are
determined as per the Package Power SKU Unit settings described in
Section 2.5.2.6.13
.
While Intel requires reading the accumulated energy data at least once every 16
seconds to ensure functional correctness, a more realistic polling rate recommendation
is once every 100mS for better accuracy. This feature assumes a 150W processor. In
general, as the power capability decreases, so will the minimum polling rate
requirement.
When determining energy changes by subtracting energy values between successive
reads, Intel advocates using the 2’s complement method to account for counter wrap-
arounds. Alternatively, adding all ‘F’s (‘0xFFFFFFFF’) to a negative result from the
subtraction will accomplish the same goal.
2.5.2.6.25
Power Limit for the VCC Power Plane Write / Read
This feature allows the PECI host to program the power limit over a specified time or
control window for the processor logic supplied by the VCC power plane. This typically
includes all the cores, home agent and last level cache. The processor does not support
power limiting on a per-core basis. Actual power limit values are chosen based on the
external VR (voltage regulator) capabilities. The units for the Power Limit and Control
Time Window are determined as per the Package Power SKU Unit settings described in
Section 2.5.2.6.13
.
Since the exact VCC plane power limit value is a function of the platform VR, this
feature is not enabled by default and there are no default values associated with the
power limit value or the control time window. The Power Limit Enable bit in
Figure 2-35
should be set to activate this feature. The Clamp Mode bit is also required to be set to
allow the cores to go into power states below what the operating system originally
requested. In general, this feature provides an improved mechanism for VR protection
Figure 2-33. Current Config Limit Read Data
Current Config Limit Data
RESERVED
13
31
Current Limit for processor VCC
12
0
Figure 2-34. Accumulated Energy Read Data
Accumulated Energy Status
Accumulated CPU Energy
0
31
