Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
53
Datasheet Volume One
2.5.2.6.18
Per Core DTS Temperature Read
This feature enables the PECI host to read the maximum value of the DTS temperature
for any specific core within the processor. Alternatively, this service can be used to read
the System Agent temperature. Temperature is returned in the same format as the
Package Temperature Read described in
Section 2.5.2.6.17
. Data is returned in relative
PECI temperature format.
Reads to a parameter value outside the supported range will return an error as
indicated by a completion code of 0x90. The supported range of parameter values can
vary depending on the number of cores within the processor. The temperature data
returned through this feature is the instantaneous value and not an averaged value. It
is updated once every 1 mS.
2.5.2.6.19
Temperature Target Read
The Temperature Target Read allows the PECI host to access the maximum processor
junction temperature (T
jmax
) in degrees Celsius. This is also the default temperature
value at which the processor thermal control circuit activates. The T
jmax
value may vary
from processor part to part to reflect manufacturing process variations. The
Temperature Target read also returns the processor T
CONTROL
value. T
CONTROL
is
returned in standard PECI temperature format and represents the threshold
temperature used by the thermal management system for fan speed control.
2.5.2.6.20
Package Thermal Status Read / Clear
The Thermal Status Read provides information on package level thermal status. Data
includes:
• Thermal Control Circuit (TCC) activation
• Bidirectional PROCHOT_N signal assertion
• Critical Temperature
Both status and sticky log bits are managed in this status word. All sticky log bits are
set upon a rising edge of the associated status bit and the log bits are cleared only by
Thermal Status reads or a processor reset. A read of the Thermal Status word always
includes a log bit clear mask that allows the host to clear any or all of the log bits that
it is interested in tracking.
A bit set to ‘0’ in the log bit clear mask will result in clearing the associated log bit. If a
mask bit is set to ‘0’ and that bit is not a legal mask, a failing completion code will be
returned. A bit set to ‘1’ is ignored and results in no change to any sticky log bits. For
example, to clear the TCC Activation Log bit and retain all other log bits, the Thermal
Status Read should send a mask of 0xFFFFFFFD.
Figure 2-30. Temperature Target Read
15
Processor Tjmax
16
T
CONTROL
8
23
RESERVED
7
0
RESERVED
31
24
