Datasheet
29
Electrical Specifications
The Yorkfield processor will operate at a 1333 MHz FSB frequency (selected by a 333
MHz BCLK[1:0] frequency). Individual processors will only operate at their specified
FSB frequency.
For more information about these signals, refer to
Section 4.2
and the appropriate
platform design guidelines.
2.9.3
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to
Table 2-3
for DC specifications. Refer to the appropriate
platform design guidelines for decoupling and routing guidelines.
Table 2-15. BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
BSEL1
BSEL0
FSB Frequency
L
L
L
RESERVED
L
L
H
RESERVED
L
H
H
RESERVED
L
H
L
RESERVED
H
H
L
RESERVED
H
H
H
RESERVED
H
L
H
RESERVED
H
L
L
333 MHz
