Intel Xeon L3360, Datasheet

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Datasheet
67
Land Listing and Signal Descriptions
DEFER# Input
DEFER# is asserted by an agent to indicate that a transaction cannot
be ensured in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or input/output agent. This
signal must connect the appropriate pins/lands of all processor FSB
agents.
DPRSTP# Input
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state. To
return to the Deep Sleep State, DPRSTP# must be deasserted. Use of
the DPRSTP# pin, and corresponding low power state, requires
chipset support and may not be available on all platforms. Refer to
the appropriate platform design guide for implementation details.
NOTE: Some processors may not have the Deeper Sleep State
enabled, refer to the Specification Update for specific sku and
stepping guidance.
DPSLP# Input
DPSLP#, when asserted on the platform, causes the processor to
transition from the Sleep State to the Deep Sleep state. To return to
the Sleep State, DPSLP# must be deasserted. Use of the DPSLP# pin,
and corresponding low power state, requires chipset support and may
not be available on all platforms. Refer to the appropriate platform
design guide for implementation details.
NOTE: Some processors may not have the Deep Sleep State enabled,
refer to the Specification Update for specific sku and stepping
guidance.
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle clocks.
This signal must connect the appropriate pins/lands of all processor
FSB agents.
DSTBN[3:0]#
Input/
Output
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
DSTBP[3:0]#
Input/
Output
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
FC0/
BOOTSELECT
Other
FC0/BOOTSELECT is not used by the Yorkfield processor. When this
land is tied to Vss previous processors based on the Intel NetBurst®
microarchitecture should be disabled and prevented from booting.
Refer to appropriate platform design guide for termination guidance.
Table 4-3. Signal Description (Sheet 4 of 10)
Name Type Description
Signals
Associated
Strobe
D[15:0]#, DBI0# DSTBN0#
D[31:16]#, DBI1# DSTBN1#
D[47:32]#, DBI2# DSTBN2#
D[63:48]#, DBI3# DSTBN3#
Signals
Associated
Strobe
D[15:0]#, DBI0# DSTBP0#
D[31:16]#, DBI1# DSTBP1#
D[47:32]#, DBI2# DSTBP2#
D[63:48]#, DBI3# DSTBP3#