Intel Xeon L3360 Datasheet Download Page 78

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Thermal Specifications and Design Considerations

Datasheet

Figure 5-1. Quad-Core Intel

Xeon

Processor 3300 Series Thermal Profile(95W)

y = 0.28x + 44.8

44.0

48.0

52.0

56.0

60.0

64.0

68.0

72.0

Power (W)

case (

)

Summary of Contents for Xeon L3360

Page 1: ...Document Number 319005 002 Quad Core Intel Xeon Processor 3300 Series Datasheet February 2009 Version 002 ...

Page 2: ...roducts processor_number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor_number for deta...

Page 3: ...ent Control Interface PECI DC Specifications 26 2 8 3 2 GTL Front Side Bus Specifications 26 2 9 Clock Specifications 28 2 9 1 Front Side Bus Clock BCLK 1 0 and Processor Clocking 28 2 9 2 FSB Frequency Select Signals BSEL 2 0 29 2 9 3 Phase Lock Loop PLL and Filter 29 2 9 4 BCLK 1 0 Specifications 30 3 Package Mechanical Specifications 33 3 1 Package Mechanical Specifications 33 3 1 1 Package Mec...

Page 4: ... Snoop State 90 6 2 5 Enhanced Intel SpeedStep Technology 90 6 2 6 Processor Power Status Indicator PSI Signal 90 7 Boxed Processor Specifications 91 7 1 Introduction 91 7 2 Mechanical Specifications 92 7 2 1 Boxed Processor Cooling Solution Dimensions 92 7 2 2 Boxed Processor Fan Heatsink Weight 94 7 2 3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly 94 7 3 Electrical Requi...

Page 5: ...eferences 11 2 1 Voltage Identification Definition 14 2 2 Absolute Maximum and Minimum Ratings 17 2 3 Voltage and Current Specifications 18 2 4 VCC Static and Transient Tolerance 19 2 5 VCC Overshoot Specifications 21 2 6 FSB Signal Groups 23 2 7 Signal Characteristics 24 2 8 Signal Reference Voltages 24 2 9 GTL Signal Group DC Specifications 24 2 10 Open Drain and TAP Output Signal Group DC Speci...

Page 6: ...istory Document Number Version Number Revision Description Revision Date 319005 1 0 001 Initial release January 2008 002 Added Quad Core Intel Xeon Processor X3380 L3360 Updated VID information Added PSI Signal February 2009 ...

Page 7: ...support Intel Virtualization Technology Virtualization Technology provides silicon based functionality that works together with compatible Virtual Machine Monitor VMM software to improve on software only solutions Available at 3 16 GHz 3 00 GHz 2 83 GHz 2 66 GHz and 2 50 GHz Quad Core Intel Xeon Processor 3300 Series Enhanced Intel Speedstep Technology Supports Intel 64 architecture Supports Intel...

Page 8: ...8 Datasheet ...

Page 9: ... several Advanced Technologies Execute Disable XD Bit Intel 64 architecture Intel 64 Enhanced Intel SpeedStep Technology and Intel Virtualization Technology Intel VT The processor s front side bus FSB utilizes a split transaction deferred reply protocol The FSB uses Source Synchronous Transfer of address and data to improve performance by transferring data four times per bus clock 4X data transfer...

Page 10: ...sors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material F...

Page 11: ...al and Mechanical Design Guidelines Addendum http www intel com products processor xeon3000 documentation htm therma l_models Quad Core Intel Xeon Processor 3300 Series Specification Update http download intel com design intarch specupdt 319007 pdf Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket http www intel com design processor applnots 31321...

Page 12: ...Introduction 12 Datasheet ...

Page 13: ...the component For further information and guidelines refer to the appropriate platform design guidelines 2 2 1 VCC Decoupling VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications This includes bulk capacitance with low effective series resistance ESR to keep the voltage rail within specifications during large swings in load curre...

Page 14: ...ocessor uses eight voltage identification signals VID 7 0 to support automatic selection of power supply voltages Table 2 1 specifies the voltage level corresponding to the state of VID 7 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 7 0 11111110 or the voltage regulation circuit cannot supply the voltage that is reque...

Page 15: ... 0 0 0 7375 0 0 1 1 0 0 1 0 1 3 1 0 0 0 1 1 1 0 0 725 0 0 1 1 0 1 0 0 1 2875 1 0 0 1 0 0 0 0 0 7125 0 0 1 1 0 1 1 0 1 275 1 0 0 1 0 0 1 0 0 7 0 0 1 1 1 0 0 0 1 2625 1 0 0 1 0 1 0 0 0 6875 0 0 1 1 1 0 1 0 1 25 1 0 0 1 0 1 1 0 0 675 0 0 1 1 1 1 0 0 1 2375 1 0 0 1 1 0 0 0 0 6625 0 0 1 1 1 1 1 0 1 225 1 0 0 1 1 0 1 0 0 65 0 1 0 0 0 0 0 0 1 2125 1 0 0 1 1 1 0 0 0 6375 0 1 0 0 0 0 1 0 1 2 1 0 0 1 1 1 1 ...

Page 16: ... motherboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the appropriate platform design guidelines All TESTHI 13 11 10 7 0 lands should be individually connected to VTT via a pull up resistor which matches the nominal trac...

Page 17: ...itions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be se...

Page 18: ... 1 3625 V 1 VCC Core Processor Number X3380 X3370 L3360 X3330 X3360 X3350 X3320 VCC for 775_VR_CONFIG_05A 95W 775_VR_CONFIG_06A 65W 3 16 GHz 12MB Cache 3 00 GHz 12MB Cache 2 83 GHz 12MB Cache 2 66 GHz 6MB Cache 2 83 GHz 12MB Cache 2 66 GHz 12MB Cache 2 50 GHz 6MB Cache Refer to Table 2 4 and Figure 2 1 V 3 4 5 VCC_BOOT Default VCC voltage for initial power up 1 10 V VCCPLL PLL VCC 5 1 50 5 ICC Pro...

Page 19: ...uideline These guidelines are for estimation purposes only See Section 2 5 for further details on FMB guidelines 7 ICC_MAX specification is based on VCC_MAX loadline Refer to Figure 2 1 for details 8 VTT must be provided via a separate voltage source and not be connected to VCC This specification is measured at the land 9 Baseboard bandwidth is limited to 20 MHz 10 This is the maximum total curren...

Page 20: ...o this loadline specification is required to ensure reliable processor operation NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 7 3 2 This loadline specification shows the deviation from the VID set point 85 0 111 0 136 0 161 90 0 117 0 143 0 169 95 0 124 0 150 0 176 100 0 130 0 157 0 183 Table 2 4 VCC Static and Tran...

Page 21: ...MAX is the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed TOS_MAX TOS_MAX is the maximum allowable time duration above VID These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands NOTES 1 VOS is measured overshoot voltage 2 TOS is measured time duration above VID Table 2 5 VCC Overshoot Specifications...

Page 22: ...equire a reference voltage GTLREF which is used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF must be generated on the motherboard see Table 2 13 for GTLREF specifications Refer to the applicable platform design guidelines for details Termination resistors RTT for GTL signals are provided on the processor silicon and are terminated to VTT Intel chipsets will also p...

Page 23: ...TL Common Clock I O Synchronous to BCLK 1 0 ADS BNR BPM 5 0 BPMb 3 0 BR0 3 DBSY DRDY HIT HITM LOCK GTL Source Synchronous I O Synchronous to assoc strobe GTL Strobes Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 CMOS A20M DPSLP DPRSTP IGNNE INIT LINT0 INTR LINT1 NMI SMI 3 STPCLK PWRGOOD SLP TCK TDI TDI_M TMS TRST BSEL 2 0 VID 7 0 PSI Open Drain Output FERR PBE IERR THERMTRIP TDO TDO_M Open...

Page 24: ...ignal Characteristics Signals with RTT Signals with No RTT A 35 3 ADS ADSTB 1 0 BNR BPRI D 63 0 DBI 3 0 DBSY DEFER DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK PROCHOT REQ 4 0 RS 2 0 TRDY A20M BCLK 1 0 BSEL 2 0 COMP 8 3 0 FERR PBE IERR IGNNE INIT ITP_CLK 1 0 LINT0 INTR LINT1 NMI MSID 1 0 PWRGOOD RESET SMI STPCLK TDO TDO_M TESTHI 13 11 10 7 0 THERMTRIP VID 6 0 GTLREF 3 0 TCK TDI TDI_M TMS TRST VTT_SEL Op...

Page 25: ...TT 0 2V 3 For Vin between 0 and VOH NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All outputs are open drain ILI Input Leakage Current N A 100 µA 7 ILO Output Leakage Current N A 100 µA 8 RON Buffer On Resistance 7 49 9 16 Ω 5 Table 2 9 GTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 Table 2 10 Open Drain and TAP Output...

Page 26: ...ed control More detailed information may be found in the Platform Environment Control Interface PECI Specification 2 8 3 2 GTL Front Side Bus Specifications In most cases termination resistors are not required as these are integrated into the processor silicon See Table 2 7 for details on which GTL signals do not include on die termination Refer to the appropriate platform design guidelines for sp...

Page 27: ...it may require different resistor values Each GTLREF land must be connected refer to the platform design guide for implementation details 3 RTT is the on die termination resistance measured at VTT 3 of the GTL output driver Refer to the appropriate platform design guide for the board impedance Refer to processor I O buffer models for I V characteristics 4 COMP resistance must be provided on the sy...

Page 28: ...ssors operate only at or below the rated frequency 2 Listed frequencies are not necessarily committed production frequencies 2 9 2 FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 2 15 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is de...

Page 29: ...e platform design guidelines 2 9 3 Phase Lock Loop PLL and Filter An on die PLL filter solution will be implemented on the processor The VCCPLL input is used for the PLL Refer to Table 2 3 for DC specifications Refer to the appropriate platform design guidelines for decoupling and routing guidelines Table 2 15 BSEL 2 0 Frequency Table for BCLK 1 0 BSEL2 BSEL1 BSEL0 FSB Frequency L L L RESERVED L L...

Page 30: ...he worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability 5 Slew rate is measured through the VSWING voltage range centered about differential zero Measurement taken from differential waveform 6 Matching applies to rising edge rate for Clock and falling edge rate for Clo...

Page 31: ...1 Tph Tpl Tp Tp T1 BCLK 1 0 period T2 BCLK 1 0 period stability not shown Tph T3 BCLK 1 0 pulse high time Tpl T4 BCLK 1 0 pulse low time T5 BCLK 1 0 rise time through the threshold region T6 BCLK 1 0 fall time through the threshold region VCROSS ABS VCROSS ABS Figure 2 4 Measurement Points for Differential Clock Waveforms 150 mV 150 mV 0 0V 0 0V Slew_rise 150mV 150mV V_swing Slew _fall Diff T5 BCL...

Page 32: ...Electrical Specifications 32 Datasheet ...

Page 33: ... solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket The package components shown in Figure 3 1 include the following 1 Integrated Heat Spreader IHS 2 Thermal Interface Material TIM 3 Processor core die 4 Package substrate 5 Capacit...

Page 34: ...r These dimensions include 1 Package reference with tolerances total height length width etc 2 IHS parallelism and tilt 3 Land dimensions 4 Top side and back side component keep out dimensions 5 Reference datums 6 All drawing dimensions are in mm in 7 Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the process...

Page 35: ...Datasheet 35 Package Mechanical Specifications Figure 3 2 Processor Package Drawing Sheet 1 of 3 ...

Page 36: ...Package Mechanical Specifications 36 Datasheet Figure 3 3 Processor Package Drawing Sheet 2 of 3 ...

Page 37: ...Datasheet 37 Package Mechanical Specifications Figure 3 4 Processor Package Drawing Sheet 3 of 3 ...

Page 38: ...rm compressive loading in a direction normal to the processor IHS 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum specified load on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dy...

Page 39: ...5 g 0 76 oz This mass weight includes all the components that are included in the package 3 1 7 Processor Materials Table 3 3 lists some of the package components and associated materials 3 1 8 Processor Markings Figure 3 5 shows the topside markings on the processor This diagram is to aid in the identification of the processor Table 3 3 Processor Materials Component Material Integrated Heat Sprea...

Page 40: ...ssor Land Coordinates and Quadrants Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Socket 775 Quadrants Top View VCC V...

Page 41: ...ns the land listings for the processor The land out footprint is shown in Figure 4 1 and Figure 4 2 These figures represent the land out arranged by land number and they show the physical location of each signal on the package land array top view Table 4 1 is a listing of all processor lands ordered alphabetically by land signal name Table 4 2 is also a listing of all processor lands the ordering ...

Page 42: ...Y VCC VCC VCC VCC VCC VCC VCC VCC W VCC VCC VCC VCC VCC VCC VCC VCC V VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS VSS VSS P VSS VSS VSS VSS VSS VSS VSS VSS N VCC VCC VCC VCC VCC VCC VCC VCC M VCC VCC VCC VCC VCC VCC VCC VCC L VSS VSS VSS VSS VSS VSS VSS VSS K VCC VCC VCC VCC VCC VCC VCC VCC J VCC VCC VCC VCC VCC VCC ...

Page 43: ...A21 VSS FC39 VTT_OUT_ RIGHT AA VCC VSS A19 VSS A20 PSI VSS FC0 BOOT SELECT Y VCC VSS A18 A16 VSS TESTHI1 TDI_M MSID0 W VCC VSS VSS A14 A15 VSS RSVD MSID1 V VCC VSS A10 A12 A13 FC30 FC29 TDO_M U VCC VSS VSS A9 A11 VSS FC4 COMP1 T VCC VSS ADSTB0 VSS A8 FERR PBE VSS COMP3 R VCC VSS A4 RSVD VSS INIT SMI TESTHI11 P VCC VSS VSS RSVD RSVD VSS IGNNE PWRGOOD N VCC VSS REQ2 A5 A7 STPCLK THER MTRIP VSS M VCC...

Page 44: ...Input Output ADSTB0 R6 Source Synch Input Output ADSTB1 AD5 Source Synch Input Output BCLK0 F28 Clock Input BCLK1 G28 Clock Input BNR C2 Common Clock Input Output BPM0 AJ2 Common Clock Input Output BPM1 AJ1 Common Clock Input Output BPM2 AD2 Common Clock Input Output BPM3 AG2 Common Clock Input Output BPM4 AF2 Common Clock Input Output BPM5 AG3 Common Clock Input Output BPMb0 G1 Common Clock Input...

Page 45: ...put D57 B18 Source Synch Input Output D58 C21 Source Synch Input Output D59 B21 Source Synch Input Output D6 B7 Source Synch Input Output Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction D60 B19 Source Synch Input Output D61 A19 Source Synch Input Output D62 A22 Source Synch Input Output D63 B22 Source Synch Input Output D7 A7 Source Synch Input Output D8 A10 Sou...

Page 46: ...utput REQ3 K6 Source Synch Input Output REQ4 J6 Source Synch Input Output RESERVED V2 RESERVED A20 RESERVED AC4 RESERVED AE4 Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction RESERVED AE6 RESERVED AH2 RESERVED D1 RESERVED D14 RESERVED D16 RESERVED E23 RESERVED E6 RESERVED E7 RESERVED F23 RESERVED F29 RESERVED G6 RESERVED N4 RESERVED N5 RESERVED P5 RESET G23 Common...

Page 47: ...er VCC AF19 Power Other VCC AF21 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC AF22 Power Other VCC AF8 Power Other VCC AF9 Power Other VCC AG11 Power Other VCC AG12 Power Other VCC AG14 Power Other VCC AG15 Power Other VCC AG18 Power Other VCC AG19 Power Other VCC AG21 Power Other VCC AG22 Power Other VCC AG25 Power Other VCC AG26 Power Other ...

Page 48: ... Other VCC AM15 Power Other VCC AM18 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC AM19 Power Other VCC AM21 Power Other VCC AM22 Power Other VCC AM25 Power Other VCC AM26 Power Other VCC AM29 Power Other VCC AM30 Power Other VCC AM8 Power Other VCC AM9 Power Other VCC AN11 Power Other VCC AN12 Power Other VCC AN14 Power Other VCC AN15 Power Ot...

Page 49: ...Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC T27 Power Other VCC T28 Power Other VCC T29 Power Other VCC T30 Power Other VCC T8 Power Other VCC U23 Power Other VCC U24 Power Other VCC U25 Power Other VCC U26 Power Other VCC U27 Power Other VCC U28 Power Other VCC U29 Power Other VCC U30 Power Other VCC U8 Power Other VCC V8 Power Other VCC W23...

Page 50: ... VSS AB23 Power Other VSS AB24 Power Other VSS AB25 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AB26 Power Other VSS AB27 Power Other VSS AB28 Power Other VSS AB29 Power Other VSS AB30 Power Other VSS AB7 Power Other VSS AC3 Power Other VSS AC6 Power Other VSS AC7 Power Other VSS AD4 Power Other VSS AD7 Power Other VSS AE10 Power Other VSS AE...

Page 51: ...VSS AK16 Power Other VSS AK17 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AK2 Power Other VSS AK20 Power Other VSS AK23 Power Other VSS AK24 Power Other VSS AK27 Power Other VSS AK28 Power Other VSS AK29 Power Other VSS AK30 Power Other VSS AK5 Power Other VSS AK7 Power Other VSS AL10 Power Other VSS AL13 Power Other VSS AL16 Power Other VSS ...

Page 52: ... Other VSS H10 Power Other VSS H11 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS H12 Power Other VSS H13 Power Other VSS H14 Power Other VSS H17 Power Other VSS H18 Power Other VSS H19 Power Other VSS H20 Power Other VSS H21 Power Other VSS H22 Power Other VSS H23 Power Other VSS H24 Power Other VSS H25 Power Other VSS H26 Power Other VSS H27 P...

Page 53: ...r Other VSS V7 Power Other VSS W4 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS W7 Power Other VSS Y2 Power Other VSS Y5 Power Other VSS Y7 Power Other VSS_MB_ REGULATION AN6 Power Other Output VSS_SENSE AN4 Power Other Output VSSA B23 Power Other VTT B25 Power Other VTT B26 Power Other VTT B27 Power Other VTT B28 Power Other VTT B29 Power Othe...

Page 54: ...A23 VSS Power Other AA24 VSS Power Other AA25 VSS Power Other AA26 VSS Power Other AA27 VSS Power Other AA28 VSS Power Other AA29 VSS Power Other AA3 VSS Power Other AA30 VSS Power Other AA4 A21 Source Synch Input Output AA5 A23 Source Synch Input Output AA6 VSS Power Other AA7 VSS Power Other AA8 VCC Power Other AB1 VSS Power Other AB2 IERR Asynch CMOS Output AB23 VSS Power Other AB24 VSS Power O...

Page 55: ...Power Other AE3 FC18 Power Other AE30 VSS Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AE4 RESERVED AE5 VSS Power Other AE6 RESERVED AE7 VSS Power Other AE8 SKTOCC Power Other Output AE9 VCC Power Other AF1 TDO TAP Output AF10 VSS Power Other AF11 VCC Power Other AF12 VCC Power Other AF13 VSS Power Other AF14 VCC Power Other AF15 VCC Power Other AF16 ...

Page 56: ...CC Power Other AH19 VCC Power Other AH2 RESERVED Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AH20 VSS Power Other AH21 VCC Power Other AH22 VCC Power Other AH23 VSS Power Other AH24 VSS Power Other AH25 VCC Power Other AH26 VCC Power Other AH27 VCC Power Other AH28 VCC Power Other AH29 VCC Power Other AH3 VSS Power Other AH30 VCC Power Other AH4 A32 Source Synch...

Page 57: ...r AK8 VCC Power Other AK9 VCC Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AL1 FC25 Power Other AL10 VSS Power Other AL11 VCC Power Other AL12 VCC Power Other AL13 VSS Power Other AL14 VCC Power Other AL15 VCC Power Other AL16 VSS Power Other AL17 VSS Power Other AL18 VCC Power Other AL19 VCC Power Other AL2 PROCHOT Asynch CMOS Input Output AL20 VSS P...

Page 58: ...nt Land Land Name Signal Buffer Type Direction AN26 VCC Power Other AN27 VSS Power Other AN28 VSS Power Other AN29 VCC Power Other AN3 VCC_SENSE Power Other Output AN30 VCC Power Other AN4 VSS_SENSE Power Other Output AN5 VCC_MB_ REGULATION Power Other Output AN6 VSS_MB_ REGULATION Power Other Output AN7 VID_SELECT Power Other Output AN8 VCC Power Other AN9 VCC Power Other B1 VSS Power Other B10 D...

Page 59: ... Source Synch Input Output D12 VSS Power Other D13 D25 Source Synch Input Output Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction D14 RESERVED D15 VSS Power Other D16 RESERVED D17 D49 Source Synch Input Output D18 VSS Power Other D19 DBI2 Source Synch Input Output D2 ADS Common Clock Input Output D20 D48 Source Synch Input Output D21 VSS Power Other D22 D46 Source Sy...

Page 60: ...ignal Buffer Type Direction F7 VSS Power Other F8 D17 Source Synch Input Output F9 D18 Source Synch Input Output G1 BPMb0 Common Clock Input Output G10 GTLREF3 Power Other Input G11 DBI1 Source Synch Input Output G12 DSTBN1 Source Synch Input Output G13 D27 Source Synch Input Output G14 D29 Source Synch Input Output G15 D31 Source Synch Input Output G16 D32 Source Synch Input Output G17 D36 Source...

Page 61: ...er Other J22 VCC Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction J23 VCC Power Other J24 VCC Power Other J25 VCC Power Other J26 VCC Power Other J27 VCC Power Other J28 VCC Power Other J29 VCC Power Other J3 FC22 Power Other J30 VCC Power Other J4 VSS Power Other J5 REQ1 Source Synch Input Output J6 REQ4 Source Synch Input Output J7 VSS Power Other J8 VC...

Page 62: ...5 RESERVED N6 VSS Power Other N7 VSS Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction N8 VCC Power Other P1 TESTHI11 Power Other Input P2 SMI Asynch CMOS Input P23 VSS Power Other P24 VSS Power Other P25 VSS Power Other P26 VSS Power Other P27 VSS Power Other P28 VSS Power Other P29 VSS Power Other P3 INIT Asynch CMOS Input P30 VSS Power Other P4 VSS Powe...

Page 63: ...ther V30 VSS Power Other V4 A15 Source Synch Input Output V5 A14 Source Synch Input Output Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction V6 VSS Power Other V7 VSS Power Other V8 VCC Power Other W1 MSID0 Power Other Output W2 TDI_M Power Other Input W23 VCC Power Other W24 VCC Power Other W25 VCC Power Other W26 VCC Power Other W27 VCC Power Other W28 VCC Power Oth...

Page 64: ...orted in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 signals All bus agents observe t...

Page 65: ...r FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI BR0 Input Output BR0 drives the BREQ0 signal in the system and is used by the processor to requ...

Page 66: ...the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBR Output DBR Debug Reset is used only in processor systems where no debug port is implemented on the system b...

Page 67: ... power state requires chipset support and may not be available on all platforms Refer to the appropriate platform design guide for implementation details NOTE Some processors may not have the Deep Sleep State enabled refer to the Specification Update for specific sku and stepping guidance DRDY Input Output DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data o...

Page 68: ...LREF is used by the GTL receivers to determine if a signal is a logical 0 or logical 1 Refer to the applicable platform design guide for more information HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting...

Page 69: ...I INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these signals as LINT 1 0 is the default configuration LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins lands of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transac...

Page 70: ...e reached their proper specifications On observing active RESET all FSB agents will de assert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have ...

Page 71: ...tails THERMTRIP Output In the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature approximately 20 C above the maximum TC Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur Upon assertion of THERMTRIP the processor will shut off...

Page 72: ...VCC to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals becomes valid The VID signals are needed to support the processor voltage specification variations See Table 2 1 for definitions of these signals The VR must supply the voltage that is requested by the signals or disable itself VID_SELECT Output This land is tied high on the processor packag...

Page 73: ...y for some signals that require termination to VTT on the motherboard Refer to the appropriate platform design guide for details on implementation VTT_SEL Output The VTT_SEL signal is used to select the correct VTT voltage level for the processor This land is connected internally in the package to VSS Table 4 3 Signal Description Sheet 10 of 10 Name Type Description ...

Page 74: ...Land Listing and Signal Descriptions 74 Datasheet ...

Page 75: ... per frequency in Table 5 1 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design refer to the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum The processor uses a methodology for managing processor temperatures which is intended to support acousti...

Page 76: ...or the processor to remain within specification NOTES 1 Specification is at 37 C Tc and minimum voltage loadline Specification is guaranteed by design characterization and not 100 tested 2 Thermal Design Power TDP should be used for processor thermal solution design targets The TDP is not the maximum power that the processor can dissipate 3 This table shows the maximum TDP for a given frequency ra...

Page 77: ... 8 50 58 8 2 45 4 52 59 4 4 45 9 54 59 9 6 46 5 56 60 5 8 47 0 58 61 0 10 47 6 60 61 6 12 48 2 62 62 2 14 48 7 64 62 7 16 49 3 66 63 3 18 49 8 68 63 8 20 50 4 70 64 4 22 51 0 72 65 0 24 51 5 74 65 5 26 52 1 76 66 1 28 52 6 78 66 6 30 53 2 80 67 2 32 53 8 82 67 8 34 54 3 84 68 3 36 54 9 86 68 9 38 55 4 88 69 4 40 56 0 90 70 0 42 56 6 92 70 6 44 57 1 94 71 1 46 57 7 95 71 4 48 58 2 ...

Page 78: ...ations and Design Considerations 78 Datasheet Figure 5 1 Quad Core Intel Xeon Processor 3300 Series Thermal Profile 95W y 0 28x 44 8 44 0 48 0 52 0 56 0 60 0 64 0 68 0 72 0 0 10 20 30 40 50 60 70 80 90 Power W Tcase C ...

Page 79: ... Maximum Tc C Power W Maximum Tc C 0 49 6 34 63 54 2 50 42 36 64 36 4 51 24 38 65 18 6 52 06 40 66 8 52 88 42 66 82 10 53 7 44 67 64 12 54 52 46 68 46 14 55 34 48 69 28 16 56 16 50 70 1 18 56 98 52 70 92 20 57 8 54 71 74 22 58 62 56 72 56 24 59 44 58 73 38 26 60 26 60 74 2 28 61 08 62 75 02 30 61 9 64 75 84 32 62 72 65 76 25 Thermal Profile 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 Power W ...

Page 80: ...manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Clocks often will not be off for more than 3 0 m...

Page 81: ...ating point represents the normal operating condition for the processor Under this condition the core frequency to FSB multiple utilized by the processor is that contained in the CLK_GEYSIII_STAT MSR and the VID is that specified in Table 2 3 These parameters represent normal system operation The second operating point consists of both a lower operating frequency and voltage When the TCC is activa...

Page 82: ...software usage of this mechanism to limit the processor temperature If bit 4 of the ACPI P_CNT Control Register located in the processor IA32_THERM_CONTROL MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock mod...

Page 83: ... allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that...

Page 84: ... represents the delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT assertions As the temperature approaches TCC activation the PECI value approaches zero TCC activates at a PECI count of zero 5 3 2 PECI Specifications 5 3 2 1 PECI Device Address The PECI register resides at address 0x30 5 3 2 2 PECI Command Support PECI command support is covered in detail in t...

Page 85: ...perational or safety issues due to an abnormal condition on PECI the Host controller should take action to protect the system from possible damage It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive GetTemp s or for a one second time interval The host con...

Page 86: ...Thermal Specifications and Design Considerations 86 Datasheet ...

Page 87: ...tion 2 Address signals not identified in this table as configuration options should not be asserted during RESET 3 Disabling of any of the cores within a Yorkfield processor must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR will allow for the disabling of a single core per die within the Yorkfield package 6 2 Clock Control and Low Power States The processor allows ...

Page 88: ...ocessor continues normal operation The halted core will transition to the Normal state upon the occurrence of SMI INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the Intel Architecture Software Developer s Manual Volume 3B System Programm...

Page 89: ...lue and then change the bus ratio back to the original value 6 2 3 Stop Grant State When the STPCLK signal is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Since the GTL signals receive power from the FSB these signals should not be driven allowing the level to return to VTT for mini...

Page 90: ...own in Figure 6 1 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system Note that the fro...

Page 91: ...chapter are dimensioned in millimeters and inches in brackets Figure 7 1 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solu...

Page 92: ...flow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 7 2 Side View and Figure 7 3 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 7 7 and Figure 7 8 Note that some figures have cen...

Page 93: ...t show the attached hardware for the clip design and is provided only as a mechanical representation Figure 7 3 Top View Space Requirements for the Boxed Processor Boxed_Proc_TopView 95 0 3 74 95 0 3 74 Figure 7 4 Overall View Space Requirements for the Boxed Processor ...

Page 94: ... processor Table 7 1 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides VOH to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the S...

Page 95: ... draw Fan start up current draw maximum duration 1 2 0 5 2 2 1 0 A A A Second SENSE SENSE frequency 2 pulses per fan revolution 1 NOTES 1 Baseboard should pull this pin up to 5V with a resistor CONTROL 21 25 28 kHz 2 3 2 Open drain type pulse width modulated 3 Fan will have pull up resistor for this signal to maximum of 5 25 V Pin Signal 1 2 3 4 1 2 3 4 GND 12 V SENSE CONTROL Straight square pin 4...

Page 96: ... Table 5 1 in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflo...

Page 97: ...Datasheet 97 Boxed Processor Specifications Figure 7 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view ...

Page 98: ...hat point the fan speed is at its maximum As fan speed increases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point These set points represented in Figure 7 9 and Table 7 2 can vary by a few degrees from fan heatsink to fan heatsink The internal chassis temperature should be kept below 38 ºC M...

Page 99: ...of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures Figure 7 9 Boxed Processor Fan Heatsink Set Points Table 7 2 Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point ºC Boxed Processor Fan Spe...

Page 100: ...rolled mode allowing compatibility with existing 3 pin baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control see the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum ...

Page 101: ...r socket and the Yorkfield processor The LAI lands plug into the processor socket while the Yorkfield processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the Yorkfield processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions shoul...

Page 102: ...Debug Tools Specifications 102 Datasheet ...

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