Datasheet
71
Land Listing and Signal Descriptions
STPCLK#
Input
STPCLK# (Stop Clock), when asserted, causes the processor to enter
a low power Stop-Grant state. The processor issues a Stop-Grant
Acknowledge transaction, and stops providing internal clock signals
to all processor core units except the FSB and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is de-asserted, the
processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI, TDI_M
Input
TDI and TDI_M (Test Data In) transfers serial test data into the
processor. TDI and TDI_M provide the serial input needed for JTAG
specification support. TDI connects to core 0. TDI_M connects to core
1. Refer to the appropriate platform design guide for more
information.
TDO, TDO_M
Output
TDO and TDO_M (Test Data Out) transfers serial test data out of the
processor. TDO and TDO_M provide the serial output needed for JTAG
specification support. TDO connects to core 1. TDO_M connects to
core 0. Refer to the appropriate platform design guide for more
information.
TESTHI[13,
11:10,7:0]
Input
TESTHI[13,11:10,7:0] must be connected to the processor’s
appropriate power source (refer to VTT_OUT_LEFT and
VTT_OUT_RIGHT signal description) through a resistor for proper
processor operation. See
Section 2.4
for more details.
THERMTRIP#
Output
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a temperature
approximately 20 °C above the maximum T
C
. Assertion of
THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond where permanent silicon
damage may occur. Upon assertion of THERMTRIP#, the processor
will shut off its internal clocks (thus, halting program execution) in an
attempt to reduce the processor junction temperature. To protect the
processor, its core voltage (V
CC
) must be removed following the
assertion of THERMTRIP#. Driving of the THERMTRIP# signal is
enabled within 10
µ
s of the assertion of PWRGOOD (provided V
TT
and
V
CC
are asserted) and is disabled on de-assertion of PWRGOOD (if V
TT
or V
CC
are not valid, THERMTRIP# may also be disabled). Once
activated, THERMTRIP# remains latched until PWRGOOD, V
TT
or V
CC
is de-asserted. While the de-assertion of the PWRGOOD, V
TT
or V
CC
signal will de-assert THERMTRIP#, if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will
again be asserted within 10
µ
s of the assertion of PWRGOOD
(provided V
TT
and V
CC
are valid).
TMS
Input
TMS (Test Mode Select) is a JTAG specification support signal used by
debug tools.
TRDY#
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
TRST#
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset. Refer to the Debug Port
Design Guide for UP / DP Systems for complete implementation
details.
Table 4-3.
Signal Description (Sheet 8 of 10)
Name
Type
Description
