Thermal Specifications and Design Considerations
84
Datasheet
5.3.1.1
T
CONTROL
and TCC activation on PECI-Based Systems
Fan speed control solutions based on PECI utilize a T
CONTROL
value stored in the
processor IA32_TEMPERATURE_TARGET MSR. The T
CONTROL
MSR uses the same offset
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the T
CONTROL
value as negative. Thermal management algorithms
should utilize the relative temperature value delivered over PECI in conjunction with the
T
CONTROL
MSR value to control or optimize fan speeds.
Figure 5-5
shows a conceptual
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
5.3.2
PECI Specifications
5.3.2.1
PECI Device Address
The PECI register resides at address 0x30.
5.3.2.2
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Please refer to this document for details on supported PECI
command function and codes.
5.3.2.3
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
Figure 5-5. Conceptual Fan Control Diagram on PECI-Based Platforms
