Intel® SRMK2 Internet Server Technical Product Specification
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AP is protected, and does not get overwritten. Failure to comply with these guidelines
will result in a system hang during the next SMI.
7.3.1.2.3
Multiple Processor speed support
The SRMK2 BIOS supports numerous versions of Pentium
®
III
without the need to
reflash the BIOS. Two processor modules of different operating frequencies are not
allowed within a single system configuration. All installed processors must run at the
same frequency (for example, the bus and core frequencies of all processors must be
identical). Also, for best performance, all processors should be of the same revision.
Additionally, the processors in the system must be run at the same speed.
!
!
NOTE
The BIOS setup reports the type and speed of all detected and enabled processors. If
the BIOS detects processor speed mismatches, it will disable processors, starting with
the slowest processor, until the mismatch has been eliminated. In the worst case, only
one processor will be enabled. The BIOS will issue a POST error indicating a
mismatch in processor speeds.
7.3.1.3
Memory Sizing
During POST the BIOS:
•
Tests and sizes memory
•
Configures the memory controller
SRMK2 supports various sizes and configurations of ECC SDRAM DIMMs. Memory sizing and
configuration are only guaranteed for qualified DIMMs. The BIOS gathers all type, size, speed
and memory attributes from the on-board EEPROM or SPD on the memory DIMM. The
memory must be stuffed from the lowest DIMM socket to the highest for the memory to work in
all configurations over the full environmental range of the server.
The memory-sizing algorithm determines the size of each row of DIMMs. The BIOS reads the
DIMM speed information and programs the PAC accordingly. The BIOS always initializes ECC
memory. The BIOS is capable of reporting up to 64 MB using INT 15h, AH = 88h, or 4096 MB
using INT 15h, function E801h. INT 15h, function E820h supports reporting of the system
memory regions.
7.3.1.4
Boot Device Selection
The BIOS adheres to the
BIOS Boot Specification
(BBS). See Section 14.2 for information
about this specification. A boot device other than the one specified by the BBS may be selected
during recovery from boot failures.
7.3.1.5
Processor Microcode Update API
The Pentium
®
III
processor has the capability to correct specific errata through the loading of an
Intel supplied data block. The
Pentium
®
Pro Processor BIOS Update
Specification
defines a
way to incorporate future releases of such a data block (also called the “update”) into a system
BIOS. The BIOS is responsible for storing the update in a non-volatile memory block and loading
it into the Pentium
®
III
processor during POST sequence. The Pentium
®
Pro processor BIOS
update specification requires the system BIOS to implement function calls to read the update and
