Intel® SRMK2 Internet Server Technical Product Specification
33
calendar with alarm features and century rollover. The real-time clock supports 256 bytes of
battery-backed CMOS SRAM in two banks that are reserved for BIOS use.
A coin-cell battery powers the real-time clock and CMOS memory. When the computer is not
plugged into a wall socket, the battery has an estimated life of three years. When the computer is
plugged in, the 3.3V standby current from the power supply extends the life of the battery. The
clock is accurate to
±
13 minutes/year at 25ºC with 3.3VSB applied. The time, date, and CMOS
values can be specified in the BIOS Setup program.
!
NOTE
The recommended method of accessing the date in systems with Intel
®
serverboards is indirectly from the
Real Time Clock (RTC) via the BIOS. The BIOS on Intel
®
serverboards contains a century checking and
maintenance feature. This feature checks the two least significant digits of the year stored in the RTC
during each BIOS request (INT 1Ah) to read the date and, if less than 80 (i.e., 1980 is the first year supported
by the PC), updates the century byte to 20. This feature enables operating systems and applications using
the BIOS date/time services to reliably manipulate the year as a four-digit value.
For more information on a proper date access in systems with Intel serverboards, please visit:
http://support.intel.com/support/year2000/
3.10 Intel
®
82559 10/100 Ethernet Controllers
Two Intel 82559 LAN controllers provide two 10/100 Base-T RJ-45 interfaces. The two LAN
ports are brought out through a double stacked RJ45 connector on the rear of the chassis.
The LAN circuitry supports Wake on LAN technology on both LAN ports. Wake on LAN
technology enables remote wakeup of the computer through a network. If a PCI add-in network
interface card (NIC) with remote wakeup capabilities is desired, the remote wakeup connector on
the NIC must be connected to the onboard Wake on LAN header at J8. The on-board LAN
controllers or an add-in NIC will monitor network traffic at the MII interface; upon detecting a
Magic Packet† the LAN controllers or NIC will assert a wakeup signal that will power up the
computer. Alert and wake on LAN features are supported by the SRMK2 and the SMBus
interface of the Intel 82559s.
CAUTION
For Wake on LAN, the +5V standby line for the power supply must be capable of deli5V
±
5% at
720mA. Failure to provide adequate standby current when implementing Wake on LAN can damage the
power supply.
3.11 Video Interface
The on-board video interface is implemented using the ATI RAGE XL video controller. The
video controller is accessed over the 32-bit PCI bus interface on the ServerWorks
®
North Bridge.
Some of the key features of the video interface are listed below:
•
Comprehensive AGP support, including 2X mode, Sideband addressing.
•
Fully PC 98 compliant.
•
32-bit wide memory-mapped registers.
•
Programmable flat or paged memory model with linear frame buffer access.
•
Triple 8-bit palette DAC with gamma correction for true WYSIWYG color.
•
Pixel rates up to 230 MHz.
