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Intel SRMK2 - Server Platform - 0 MB RAM Technical Specifications Download Page 68

 

Intel® SRMK2 Internet Server Technical Product Specification

 

68

 

204h 

MTRRphysBase2 

Physical Address Base 2 

0000h 

205h 

MTRRphysMask2 

Physical Address Mask 2 

0000h 

206h 

MTRRphysBase3 

Physical Address Base 3 

0000h 

207h 

MTRRphysMask3 

Physical Address Mask 3 

0000h 

208h 

MTRRphysBase4 

Physical Address Base 4 

0000h 

209h 

MTRRphysMask4 

Physical Address Mask 4 

0000h 

20Ah 

MTRRphysBase5 

Physical Address Base 5 

0000h 

20Bh 

MTRRphysMask5 

Physical Address Mask 5 

0000h 

20Ch 

MTRRphysBase6 

Physical Address Base 6 

0000h 

20Dh 

MTRRphysMask6 

Physical Address Mask 6 

0000h 

20Eh 

MTRRphysBase7 

Physical Address Base 7 

0000h 

20Fh 

MTRRphysMask7 

Physical Address Mask 7 

0000h 

250h 

MTRRfix64k_00000 

Fixed range for 00h - 7Fh segment in 64KB block 

0606060606060606h 

258h 

MTRRfix16k_80000 

Fixed range for 80h - 9Fh segment in 16KB block 

0606060606060606h 

259h 

MTRRfix16k_A0000 

Fixed range for A0h - BFh segment in 16KB block 

0000h 

268h 

MTRRfix4k_C0000 

Fixed range for C0h segment in 4KB block 

0000h 

269h 

MTRRfix4k_C8000 

Fixed range for C8h segment in 4KB block 

0000h 

26Ah 

MTRRfix4k_D0000 

Fixed range for D0h segment in 4KB block 

0000h 

26Bh 

MTRRfix4k_D8000 

Fixed range for D8h segment in 4KB block 

0000h 

26Ch 

MTRRfix4k_E0000 

Fixed range for E0h segment in 4KB block 

0000h 

26Dh 

MTRRfix4k_E8000 

Fixed range for E8h segment in 4KB block 

0000h 

26Eh 

MTRRfix4k_F0000 

Fixed range for F0h segment in 4KB block 

0505050505050505h 

26Fh 

MTRRfix4k_F8000 

Fixed range for F8h segment in 4KB block 

0505050505050505h 

2FFh 

MTRRdefType 

Default memory type and global enable flags 

00C00h 

 

7.3.2.2 

Cache State on Boot 

The BIOS looks at a bit in CMOS to determine if the system cache should be enabled or disabled.  
If the cache is enabled, the cache controller in the processor is initialized in a consistent manner 
consistent with the chipset. 
 

7.3.2.3 

Option ROM Shadowing 

All on-board adapter ROMs (stored in compressed form in the system Flash ROM), and PCI 
adapter ROMs are shadowed into RAM in the ISA-compatible ROM adapter memory space 
between C0000h to DFFFFh.  PCI BIOS ROMs are always shadowed.  Typically, the video 
BIOS is shadowed at C0000h if a video controller is present. 
 

7.3.2.4 

Memory Speed Optimization 

The BIOS detects the system memory speed and bus speed and optimizes the memory controller 
for the best performance.  The system bus speed can be determined by using the processor 
internal speed and the bus ratio.  The memory DIMM speed can be determined using its ID.  
Using this information the BIOS can set up the memory controller register for the best 
performance. 
 

Summary of Contents for SRMK2 - Server Platform - 0 MB RAM

Page 1: ...wn as errata which may cause the product to deviate from published specifications Current characterized errata are documented in the Intel SRMK2 Internet Server Specification Update February 26 2001 iPN A39185 001 Intel SRMK2 Internet Server Technical Product Specification ...

Page 2: ...for use in medical life saving or life sustaining applications Intel retains the right to make changes to specifications and product descriptions at any time without notice The Intel SRMK2 Internet Server may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local I...

Page 3: ...s detailed technical information about the SRMK2 Internet Server and its internal components This information is intended for xSPs OEM engineers vendors system integrators and other engineers and technicians who need this level of information It is not intended for general audiences Typographical Conventions This section describes the conventions used in this specification Not all of these symbols...

Page 4: ...Intel SRMK2 Internet Server Technical Product Specification iv Blank Page Prevention words ...

Page 5: ... 3 4 CHIPSET 28 3 4 1 ServerWorks CNB30LE North Bridge Chip 28 3 4 2 ServerWorks OSB4 South Bridge Chip 29 3 5 MEMORY 30 3 6 SCSI HOST BUS INTERFACE 31 3 6 1 SCSI Hard Drive LED Connector Optional 31 3 7 IDE INTERFACE 31 3 8 USB 31 3 9 I O CONTROLLER 32 3 9 1 Serial Port 32 3 9 2 Diskette Drive Controller 32 3 9 3 Keyboard and Mouse Interface 32 3 9 4 Real Time Clock CMOS SRAM and Battery 32 3 10 ...

Page 6: ...59 7 BIOS DESCRIPTION 61 7 1 OVERVIEW 61 7 2 SYSTEM BIOS 61 7 2 1 Configuration Utility 62 7 2 2 CMOS Configuration RAM Summary 62 7 2 3 Flash Memory Update Utility 62 7 2 4 Fail Safe BIOS Extensions 62 7 2 5 System Flash ROM Layout 62 7 3 SYSTEM BIOS 63 7 3 1 Auto Configuration Features 63 7 3 2 Performance Features 67 7 3 3 Reliability Features 69 7 3 4 System Services 71 7 3 5 Boot Options 74 7...

Page 7: ...OMAGNETIC COMPATIBILITY EMC REGULATIONS 97 11 3 ELECTROMAGNETIC COMPATIBILITY NOTICES SRMK2S 98 11 3 1 Japan 98 11 3 2 Canada 98 11 3 3 FCC emissions disclaimer Class A USA 98 11 3 4 Taiwan BSMI 99 11 4 ELECTROMAGNETIC COMPATIBILITY NOTICES SRMK2D 99 11 4 1 Japan 99 11 4 2 Canada 99 11 4 3 FCC emissions disclaimer class B USA 99 11 5 FCC DECLARATION OF CONFORMITY 100 11 5 1 SRMK2D 100 11 5 2 Taiwa...

Page 8: ... DCD Data Carrier Detect DEMKO Danishe Elektriske Materiellkontroll Danish Board of Testing and Approval of Electrical Equipment DIMM Dual Inline Memory Module DMA Direct Memory Access DRAM Dynamic Random Access Memory ECC Error Correction Code EDO Extended Data Out EEPROM Electrically Erasable Programmable Read Only Memory EMC Electromagnetic Compatibility EMI Electromagnetic Interference EN Euro...

Page 9: ...r Correction OSB4 PCI ISA IDE Xcelerator controller PIO Programmed Input Output PLD Programmable Logic Device POST Power On Self Test PPGA Plastic Pin Grid Array PXE Preboot Execution Environment RAM Random Access Memory RPM Revolutions Per Minute RxD Receive Data SBE Single bit Error SCL Serial Clock SCSI Small Computer Systems Interface SDA Serial Data SE Single Ended SEEPROM Serial Electrically...

Page 10: ...n x VCCI Voluntary Control Council for Interference by data processing and electronic office equipment Vdc Volts direct current Vin Volts in VRM Voltage Regulator Module Vrms Volts root mean square W Watts Wdc Watts direct current WOL Wake on LAN WOR Wake on Ring ZIF Zero Insertion Force ...

Page 11: ...or sliding rails optional Hard disk capacity Support for two 1 U160 Hot Swappable SCSI hard drives for internal configuration along with an external SCSI channel for external drives Peripheral bays Single standard slim diskette drive included with system Optional slim line CD ROM drive available works in conjunction with the standard diskette Peripheral Interfaces Two Ultra 160 SCSI channels one i...

Page 12: ...Intel SRMK2 Internet Server Technical Product Specification 12 This page was intentionally left blank ...

Page 13: ...using the two right angle midmount or front mount brackets provided with the base system that attach to the chassis and two brackets that attach to the rack It can also be installed in a standard 19 rack using a sliding rails kit Optional Table 2 Chassis dimensions Height 1 70 1U Width 16 75 between the slide mounting surfaces Depth 24 including bezel 22 41 from front mounting flange to the rear p...

Page 14: ...reveals the floppy and CD ROM bays See Figure 3 for button placement See Section 5 Front Panel Board for a complete description of the buttons and LEDs Figure 2 Front view of chassis with bezel on Additionally the front bezel can be removed to reveal the front of the chassis To access the hot swappable SCSI hard disk drives pivot the front panel out and to the right Figure 3 shows the chassis with...

Page 15: ...rofile PCI slot B Video E Serial Port A H Full Length PCI slot C Dual RJ 45 F U160 SCSI I Power Supply The power supply in the SRMK2D has a different connector Figure 5 Rear view of chassis 2 2 Internal Chassis Features 2 2 1 AC Power Supply The SRMK2 Internet Server can use two different power supplies one being an AC 200W version which ships with the SRMK2S model and a 48V DC 200W version that s...

Page 16: ...erver Management software that comes on the Resource CD in the accessory kit 2 2 1 3 AC Power Line The system is specified to operate over two input voltage ranges that are automatically selected and rated from 100 120VAC and 200 240VAC at 50 or 60Hz The power supply incorporates Power Factor Correction PFC as a standard feature The system is tested to meet these line voltages and has been tested ...

Page 17: ...er supply connectors at connector J27 and J39 Ground Ground Ground Ground VRM Input Voltage 3 3V Ground Ground 5VSB 1 13 12 24 Ground Ground 3 3V 3 3V 3 3V Ground Ground Ground VRM Input Voltage VRM Input Voltage VRM Input Voltage 5V 5V 12V Ground Figure 6 DC connector pinout J27 12V Ground 1 6 HECALERT Ground Sense PWR_ON 5 10 SMB_Data SMB_CLK 3 3V Sense PWRGOOD 5V Sense Figure 7 DC connector pin...

Page 18: ...connector on PCB Wire lengths should vary to ensure no loops or slack wire pin 1 pin 13 P3 P4 SCSI Backplane Connector 7 75 0 25 196mm 6mm Bundle C Figure 8 DC output wire harness Table 4 Baseboard Power Connector P2 Pin Signal Name 20 AWG Wire Pin Signal Name 20 AWG Wire 1 Ground Black 13 VRM Input Red 2 Ground Black 14 VRM Input Red 3 Ground Black 15 VRM Input Red 4 Ground Black 16 VRM Input Red...

Page 19: ...supply has four phillips screws that are protected by a cover for shipping Removing the cover reveals the four screws A label should show the screw markings to be A A B B The A and A connectors can be attached to a primary power source for the server while the B and B leads can be connected to a secondary power source for redundant power sourcing in case of primary source failure Table 7 shows the...

Page 20: ...64 83 W 2 2 4 System Cooling Nine 40mm fans provide cooling for the system Two of the nine fans are dedicated to cooling the power supply Six of the fans provide cooling for the processor memory and serverboard One fan cools the full length PCI slot this last fan is 40mm x 17mm and is a bit thinner than the other 40mm x 28mm fans A two speed control circuit powers the fans and is located on the SC...

Page 21: ...ng the carrier from the drive bay A pair of LEDs on the front panel flash green to indicate drive activity for each drive LED s 8 and 9 In addition the two SCSI HDD bays are hot swappable 2 2 6 System Interconnection 2 2 6 1 System Internal Cables Table 11 lists the internal cables within the system An italicized item is an optional accessory kit and is not supplied with the base system Table 11 S...

Page 22: ...m Cable Drawings Figure 9 shows drawings of all the internal cables within the system and the locations of their folds Where applicable the darker line indicates pin 1 SCSI hard drives Slim line diskette drive Front panel Slim line CD ROM drive optional Figure 9 Internal cables ...

Page 23: ...e diskette drive with bracket 1 SCSI Hot swap backplane 1 SCSI backplane cable 1 Slimline floppy diskette drive cable 1 Front panel cable 1 Fan backplane cable 1 Front and Midmount brackets 2 Heatsinks 2 Items that come in the Accessory Kit Table 13 lists optional accessories These accessories can be ordered Table 13 Optional accessories Description Product Code Qty Slim line CD ROM comes with one...

Page 24: ...faces Two integrated Intel 82559 10 100BASE T Ethernet controllers One high density diskette drive interface for slimline diskette drive Two U160 SCSI channels one internal and one external wide interface connector One IDE interface with low profile CD support One serial port Two USB ports Two PS 2 interfaces for keyboard and mouse LED panel interface One rear panel video interface Expansion Capab...

Page 25: ... Speaker Q Front panel connector E Clear Password Jumper R DIMM sockets F 64 66 PCI Bridge Connector S SCSI LED Header G ServerWorks ServerSet South Bridge T Gluechip H BIOS Flash memory U Power supply connector I Back panel I O connectors V ServerWorks ServerSet North Bridge J SMSC I O controller W Adaptec 7899 SCSI controller K Wake on Ring Header X Password override jumper L ATI Rage XL Video Y...

Page 26: ...kette Serial Port A Back Panel Keyboard Mouse Back Panel Boot Block Flash Memory Hardware Monitor SM Bus Clock Generator SDRAM DIMMs Front Panel Controller Dual 82559 Ethernet Controllers Back Panel Processor 64 66 PCI Bus Dual Slot 64 66 PCI Riser Adaptec 7899 Dual Channel SCSI Back Panel Front Drive Bay Hardware Monitor Front Panel Back Panel ATI Rage XL Video Controller USB Port 1 Figure 11 Ser...

Page 27: ...placed in the second processor PGA370 socket for UP mode operation A terminator card is shipped with the unit and is installed in the second processor socket in the factory Remove the terminator card if you wish to run in dual processor mode Table 15 lists processors supported by the SRMK2 Table 15 Processors supported by the SRMK2S serverboard Processor Type L2 Cache Size FSB Speed Speed Pentium ...

Page 28: ...e sided DIMMs 100MHz or 133MHz SDRAM Support for up to 4GB of registered SDRAM DIMM serial presence detect via SMBus interface 16 64 and 128 Mbit devices with 2 KB 4 KB and 8 KB page sizes x 4 x 8 and x 16 DRAM widths Single error correction multiple error detection Symmetrical and asymmetrical DRAM addressing ECC SEC DED PCI Bus Interface Complies with the PCI specification Rev 2 1 64 bit 33 66 M...

Page 29: ... devices PIO Mode 4 transfers at up to 16 MB sec Support for Ultra DMA 33 synchronous DMA mode transfers at up to 33 MB sec Bus master mode with an 8 x 32 bit buffer for bus master PCI IDE burst transfers Enhanced DMA controller Two 8237 based DMA controllers Support for PCI DMA with three PC PCI channels and distributed DMA protocols Fast type F DMA for reduced PCI bus usage Interrupt controller ...

Page 30: ...s imposed by the 25 degree DIMM socket spacing on the baseboard Table 16 Supported memory sizes and configurations DIMM Size Configuration DRAM Technology DRAM Depth DRAM Width Single sided DIMM Size x 64 bit Double sided DIMM Size x 64 bit 64 MB 8 Mbit x 72 64Mb 4Mb 16 bit X 8MB X 8B 64MB 64 MB 8 Mbit x 72 64Mb 8Mb 8 bit 8MB X 8B 64MB X 128 MB 16 Mbit x 72 64Mb 8Mb 8 bit X 16MB X 8B 128MB 128 MB ...

Page 31: ... the serverboard has one independent bus mastering IDE interface This interface supports ATAPI devices such as CD ROM drives ATA devices One 40 pin connector is populated on board The connector at J9 provides the primary IDE interface only this one is populated The BIOS supports logical block addressing LBA and extended cylinder head sector ECHS translation modes The drive reports the transfer rat...

Page 32: ... motherboard supports one serial port via 9 pin D Sub connector The populated serial port is located on the back panel The serial port is NS16C550 compatible UARTs and support data transfers at speeds up to 460 Kbits sec with BIOS support Additionally this port supports the Wake On Ring functionality 3 9 2 Diskette Drive Controller The I O controller supports a single diskette drive that is compat...

Page 33: ...et Controllers Two Intel 82559 LAN controllers provide two 10 100 Base T RJ 45 interfaces The two LAN ports are brought out through a double stacked RJ45 connector on the rear of the chassis The LAN circuitry supports Wake on LAN technology on both LAN ports Wake on LAN technology enables remote wakeup of the computer through a network If a PCI add in network interface card NIC with remote wakeup ...

Page 34: ...re sensor while at the same time the fan speed inputs are independently monitored Measured values from these inputs are stored in Value Registers These can be read out over the serial bus or can be compared with programmed limits stored in the Limit Registers The results of out of limit comparisons are stored in the Interrupt Status Registers and will generate an interrupt on the INT line if enabl...

Page 35: ...nternal and the power management mode being used APM or ACPI NOTE Wake on Ring and Resume on Ring technologies require the support of an operating system that provides full ACPI functionality 3 13 1 Wake on Ring The operation of Wake on Ring can be summarized as follows Powers up the computer from either the APM soft off mode or the ACPI S5 state Detects incoming calls differently for external and...

Page 36: ...32 SLOT1 P1_AD 18 00 03 NA PCI32 SLOT2 P1_AD 19 00 05 NA PCI32 LAN1 P1_AD 23 00 06 NA PCI32 LAN2 P1_AD 24 00 0F 00 OSB4 SMB Bus PCI Configuration Registers P1_AD 31 00 0F 01 OSB4 Ultra DMA IDE bus master P1_AD 31 01 02 NA PCI64 SLOT1 P2_AD 18 01 03 NA PCI 64 SLOT2 P2_AD 19 01 04 NA PCI 64 SCSI P2_AD 20 3 16 2 Interrupts Table 19 lists the system interrupts for the SRMK2 Table 19 PCI Interrupt to O...

Page 37: ...ERT GEVENT_4 Wired OR of HECETA 1 2 INT output and LAN 1 2 SMBALERT output SMBALERT GEVENT_5 Gluechip s EXTSMI output used for 5VSB errors EXTSMI GEVENT_6 Debug NMI from Front Panel or NMI jumper DBG_NMI GEVENT_7 SIO SMI SIO_SMI GEVENT_19 SIO WAKE UP SIO_WAKEUP SIO_WAKEUP 32 bit PCI SERR P1_SERR SERR 64 bit PCI SERR P2_SERR FRWP GEVNT_21 Wired OR of 32 bit PCI PME External WOL LAN1 PME and LAN2 PM...

Page 38: ...ve C0 Note At the writing of this document the PCI riser expansion boards did not have an I2 C bus ID assigned 3 17 Baseboard Connectors and Jumpers This section describes the serverboard connectors The connectors can be divided into three groups as shown in Figure 12 A B C Back panel I O connectors A Midboard connectors B Front panel connector C Figure 12 Connector groups CAUTION Only the back pa...

Page 39: ...sented by the external devices could damage the computer the interconnecting cable and the external devices themselves 3 17 1 Back Panel I O Connectors Figure 13 shows the location of the back panel I O connectors B A C D I H G E F Figure 13 Back panel I O connectors A PS 2 keyboard or mouse E LAN 1 B PS 2 keyboard or mouse F USB port 0 C Video G USB port 1 D LAN 2 H Serial Port A I 68 pin Externa...

Page 40: ... V differential USB signal USB_D 7 3 3 V differential USB signal USB_D 4 Ground 8 Ground Note J2 top is port 0 and J2 bottom is port 1 Table 24 LAN RJ45 connectors J5 Pin Signal Name Pin Signal Name 1 TX 1 TX 2 TX 2 TX 3 RX 3 RX 4 Return 4 Return 5 Return 5 Return 6 RX 6 RX 7 Return 7 Return 8 Return 8 Return Note J5 A bottom is LAN 1 and J5 B top is LAN 2 Table 25 Serial port A connector J3 Pin S...

Page 41: ...DA P0 15 GRD 16 DIFFSA 17 SCSIA_5V 18 SCSIA_5V 19 EXT_SCSI_P19_NC 20 GRD 21 ATNA 22 GRD 23 BSYA 24 ACKA 25 RSTA 26 MSGA 27 SELA 28 CDA 29 REQA 30 IOA 31 SDA 8 32 SDA 9 33 SDA 10 34 SDA 11 35 SDA 12 36 SDA 13 37 SDA 14 38 SDA 15 39 SDA P1 40 SDA 0 41 SDA 1 42 SDA 2 43 SDA 3 44 SDA 4 45 SDA 5 46 SDA 6 47 SDA 7 48 SDA P0 49 GRD 50 GRD 51 SCSIA_5V 52 SCSIA_5V 53 EXT_SCSI_P53_NC 54 GRD 55 ATNA 56 GRD 5...

Page 42: ...n LAN Header Add in board PCI bus 3 17 2 1 Peripheral Interfaces Figure 14 shows the locations of the peripheral interface connectors A B C D A High density diskette drive connector C SCSI drive connector B Primary IDE connector D SCSI LED Header Figure 14 Peripheral connectors Table 28 SCSI LED connector J35 Pin Signal Name 1 SCSI activity 2 Ground ...

Page 43: ...1 42 SDB 2 43 SDB 3 44 SDB 4 45 SDB 5 46 SDB 6 47 SDB 7 48 SDB P0 49 GRD 50 GRD 51 SCSIB_5V 52 SCSIB_5V 53 EXT_SCSI_P53_NC 54 GRD 55 ATNB 56 GRD 57 BSYB 58 ACKB 59 RSTB 60 MSGB 61 SELB 62 CDB 63 REQB 64 IOB 65 SDB 8 66 SDB 9 67 SDB 10 68 SDB 11 Table 30 High density diskette drive connector J36 Pin Signal Name Pin Signal Name 1 HEAD Side 1 Select 2 Ground 3 RDATA Read Data 4 Ground 5 WPD Write Pro...

Page 44: ... 22 Ground 23 DIOW 24 Ground 25 DIOR 26 Ground 27 DRDY 28 CSEL Cable Select pull down 29 DDAK0 DDAK1 30 Ground 31 IRQ 14 IRQ 15 32 Reserved 33 IDE_A1 Address 1 34 Reserved 35 IDE_A0 Address 0 36 IDE_A2 37 IDE_CS1 38 IDE_CS3 39 IDE_ACT 40 Ground Note Signal names in brackets are for the secondary IDE connector 3 17 2 2 Wake Headers and Power Figure 15 shows the locations of the Wake headers and pow...

Page 45: ...tion 2 2 1 4 Table 32 Wake on Ring connector J11 Pin Signal Name 1 RINGA 2 Ground Table 33 Wake on LAN connector J8 Pin Signal Name 1 5 VSB 2 Ground 3 WOL 3 17 2 3 PCI Bus Riser Card Board Figure 16 shows the location of the PCI 64 bit Riser Bus Connector A PCI 64 66 Riser Connector Figure 16 PCI 64 66 Riser Card connector A ...

Page 46: ...18 NC A69 P2_REQ64 B69 5V A19 5V B19 P2_PME A70 NC B70 5V A20 3 3V B20 NC A71 5V B71 NC A21 P2S1_INTAC B21 CK_P2_CLK2 A72 5V B72 GND A22 P2S2_INTAC B22 GND A73 GND B73 P2_CBE 6 A23 3 3V B23 CK_P2_CLK1 A74 P2_CBE 7 B74 P2_CBE 4 A24 PCI_RST B24 GND A75 P2_CBE 5 B75 GND A25 5V B25 P2_REQ 1 A76 3 3V B76 P2_AD 63 A26 P2_GNT 1 B26 P2_REQ 2 A77 P2_PAR64 B77 P2_AD 61 A27 GND B27 3 3V A78 P2_AD 62 B78 3 3V...

Page 47: ...4 3 3V B94 P2_AD 39 A44 GND B44 3 3V A95 P2_AD 40 B95 P2_AD 37 A45 P2_TRDY B45 P2_DEVSEL A96 P2_AD 38 B96 3 3V A46 GND B46 GND A97 GND B97 P2_AD 35 A47 P2_STOP B47 P2_LOCK A98 P2_AD 36 B98 P2_AD 33 A48 3 3V B48 P2_PERR A99 P2_AD 34 B99 GND A49 NC B49 3 3V A100 GND B100 NC A50 NC B50 P2_SERR A101 P2_AD 32 B101 NC A51 GND B51 3 3V ...

Page 48: ...Backplane Fan Connector B Front Panel I O Connector Figure 17 Backplane and Front panel connectors Table 35 Backplane Fan connector J37 Pin Signal Name Pin Signal Name 1 GRD 2 M_FAN1_TACH 3 GRD 4 M_FAN2_TACH 5 GRD 6 M_FAN3_TACH 7 GRD 8 M_FAN4_TACH 9 GRD 10 FAN_NC1 11 FAN_MUX 1 12 FAN_NC2 13 FAN_MUX 0 14 FAN_NC3 15 FAN_NC4 16 MAX_FANS 17 FAN_NC5 18 FAN_NC6 ...

Page 49: ...2 18 LCD_D I 19 CS2 20 FP_TYPE_BIT1 21 CS1 22 RI2 23 LED_GREEN_BLINK 24 SW1_PRESSED scroll_sw1 25 LED_YELLOW_BLINK 26 SW2_PRESSED scroll_sw2 27 LED_HDD 28 RESET_SW 29 5V Standby Power Fused 30 POWERON_SW 31 3 3V Power Fused 32 THERM_TRIP 33 SLEEP_SWITCH 34 P1_SERR NMI Switch 35 SW3_PRESSED 36 SW4_PRESSED 37 LAN1_ACTLED 38 LAN2_ACTLED 39 LAN1_LINKLED 40 LAN2_LINKLED 41 LAN1_SPEEDLED 42 LAN2_SPEEDLE...

Page 50: ...s The table below shows the jumper settings for the BIOS Setup jumper J19 This jumper is normally set with a jumper covering pins 1 2 BIOS recovery is performed by removing the jumper you need to have a BIOS diskette in the floppy disk drive or you can enter the BIOS by using the Configuration jumper setting by moving the jumper to pins 2 3 Table 37 BIOS Setup jumper J19 Function Mode Jumper Confi...

Page 51: ...ent ASM software version 1 3 which can be loaded onto any of the approved operating systems of the SRMK2 The Watchdog timer pings the ASM software at pre set intervals and waits for a response If the software does not respond within a specified period of time the Watchdog timer reboots the system and logs the error See the section entitled WatchDog Timer under the Advanced Server Management sectio...

Page 52: ... or operating frequency Maximum case temperatures are important when considering proper airflow to cool the serverboard A B C A ServerWorks ServerSet III LE South Bridge B Dual PGA370 sockets C ServerWorks ServerSet III LE North Bridge Figure 19 Thermally sensitive components CAUTION An ambient temperature that exceeds the board s maximum operating temperature by more than 5 C could cause componen...

Page 53: ...DC Voltage Regulation Table 41 shows the DC output voltages that shall remain within the regulation ranges shown which are measured at the load end of the output connectors under all line load and environmental conditions including Transients and Ripple Noise Table 41 DC output voltage regulation Output Voltage Range Min Nom Max Unit 3 3VDC 5 3 2 3 30 3 465 Volts 5 VDC 5 4 8 5 00 5 25 Volts 12 VDC...

Page 54: ... report an error message during BIOS POST see below Generally this error is seen with SCSI card adapters You will see an error message at bootup similar to the following if you have exceeded the Boot ROM space limit Error 0146 PCI Bus Number 00 Device 07 Function 0 Insufficient Memory to shadow PCI ROM You can free up Boot ROM space by either disabling the on board Adaptec 7899 SCSI Boot ROM or by...

Page 55: ...ned at startup 7 Press the Esc key several times to remove yourself from the utility and remember to save changes whenever you are prompted You can also attempt these same steps to disable the Boot ROM option on the add in cards though the steps may vary slightly depending on the card manufacturer After rebooting the machine the Insufficient Memory error should be cleared 4 4 Riser Board PCI Inter...

Page 56: ...Intel SRMK2 Internet Server Technical Product Specification 56 5 0 1 0 1 0 Figure 20 PCI riser board ...

Page 57: ...n LED LAN 1 Activity Green LED IDE CDROM Drive and SCSI Header Green LED System Fault Amber LED Power Green LED NMI Switch Serial Port B Unpopulated Figure 21 Front panel board 5 2 Front Panel Switches Table 43 gives a description of the switches buttons on the SRMK2 front panel Table 43 Front Panel switches Button Description Power On This switch is used to turn on and off power to the system Not...

Page 58: ...n a successful 10 100Mb link has occurred to an Ethernet port Once the LED is lit it blinks at a variable rate to indicate network activity on this channel LAN1 Speed Green This LED lights when the LAN1 controller has detected and is configured to run at 100 Mbps operation For 10 Mbps operation the LED will not be lit LAN2 Activity Link Green This LED lights when a successful 10 100Mb link has occ...

Page 59: ...epicts the layout of the SCSI backplane Fan 8 Power Backplane Power Connector Fan 1 Power Fan 2 Power Fan 7 Power Fan 4 Power Fan 6 Power Backplane Baseboard Conn CDROM Pwr Connector SCSI Backplane Conn Fan 9 Power Fan 5 Power SCA SCSI Conn 0 Fan 3 Power SCA SCSI Conn 1 Figure 22 SCSI Backplane Table 45 Fan 1 9 Power Connectors Pin Signal Name Wire 1 12V Yellow 2 Ground Black 3 Fan Tach Red Table ...

Page 60: ...to Baseboard Connector J10 Pin Signal Name Pin Signal Name 1 GND 11 Max Fans 2 ISC_SCL 12 GND 3 GND 13 Fan Mux 0 4 I2C_SDA 14 Fan Mux 1 5 Drive 0 Fault 15 GND 6 GND 16 Fan 4 Tach 7 Drive 1 Fault 17 Fan 3 Tach 8 Drive 0 Active 18 GND 9 GND 19 Fan 2 Tach 10 Drive 1 Active 20 Fan 1 Tach ...

Page 61: ...tion values stored in NVRAM and battery backed CMOS configuration RAM Fail Safe BIOS extensions that provide emergency remote access diagnostic and configuration capabilities to a target system Flash Memory Update Utility IFLASH EXE that loads predefined areas of Flash ROM with Setup BIOS and other code data Each of these is introduced here with references to the appropriate section for details A ...

Page 62: ...il Safe BIOS Extensions The Fail Safe BIOS extensions allow a remote user to diagnose and fix problems on a machine which has not successfully booted the OS The centerpiece of the Fail Safe extensions is the Emergency BIOS Console The Emergency BIOS Console is a Flash ROM resident utility that redirects input and output over a serial or modem connection This console is only available when the syst...

Page 63: ...port for auto configuration of the following Plug and Play SMP initialization Memory sizing Boot drive selection PS 2 Mouse and keyboard swapping Multi processor support Pentium III processor BIOS update USB keyboard and mice Boot Splash Screen 7 3 1 1 Plug and Play The BIOS supports the following industry standards for full Plug and Play capabilities Plug and Play PnP ISA specification System Man...

Page 64: ...each PCI bus in low to high sequence The PCI buses are also scanned in the same order The BIOS programs the PCI ISA interrupt routing logic in the OSB4 to steer PCI interrupts to compatible ISA IRQ s Drivers and OS programs can determine the installed devices and their assigned resources using the BIOS interface functions The BIOS does not support devices behind PCI to PCI bridges that require map...

Page 65: ...sor support Pentium III processors have a protocol based on microcode MP initialization On reset the Pentium III processors compete to become the BootStrap Processor BSP If a serious error is detected during the Built In Self Tests BIST that processor does not participate in the initialization protocol A single processor that successfully passes BIST is automatically selected by the hardware as th...

Page 66: ...teed for qualified DIMMs The BIOS gathers all type size speed and memory attributes from the on board EEPROM or SPD on the memory DIMM The memory must be stuffed from the lowest DIMM socket to the highest for the memory to work in all configurations over the full environmental range of the server The memory sizing algorithm determines the size of each row of DIMMs The BIOS reads the DIMM speed inf...

Page 67: ...re scanned Since option ROMs expect the video to be in text mode the BIOS emulates text mode The option ROM screen is restored if the user presses Escape key The ROM screen is restored if the BIOS detects any key combination including control or alt key during option ROM scan because many option ROMs employ such a key combination to enter their setup While the splash logo is displayed the video is...

Page 68: ... block 0000h 26Ch MTRRfix4k_E0000 Fixed range for E0h segment in 4KB block 0000h 26Dh MTRRfix4k_E8000 Fixed range for E8h segment in 4KB block 0000h 26Eh MTRRfix4k_F0000 Fixed range for F0h segment in 4KB block 0505050505050505h 26Fh MTRRfix4k_F8000 Fixed range for F8h segment in 4KB block 0505050505050505h 2FFh MTRRdefType Default memory type and global enable flags 00C00h 7 3 2 2 Cache State on ...

Page 69: ...dividual DIMMs and disables a DIMM that is slower than what the hardware requires while displaying a warning message 7 3 3 2 Memory Configuration Algorithm The algorithm for determining memory configuration is as follows 1 If there is no DIMM population or the DIMMs are defective or have the wrong speed then the BIOS sounds a beep code error and POST is terminated At least 4 MB of good memory is r...

Page 70: ...nsuming operation and might affect correct functioning of certain operating systems If MBEs are detected the BIOS SMI handler will log an event into the SEL System Event Log and then generate an NMI to the OS 7 3 3 5 Logging System Events The BIOS can log critical and informational events to nonvolatile memory This area is managed by the BIOS and can be accessed by an OS NVRAM driver A critical ev...

Page 71: ...1 7 3 4 System Services The BIOS provides an interface using the software interrupt 15h to report system configuration information to application programs or the OS Table 52 shows functions provided by the BIOS in addition to the IBM AT standard INT 15h functions ...

Page 72: ... 50 New Cache Services Call With Description AH Dah AL 12h CL 0 Disable Cache CL 1 Enable Cache CL 2 Read Cache Status CL 3 Set Writeback Mode CL 4 Set Write through Mode Returns Description AH bit 0 0 Disable Cache 1 Enable Cache AH bit 1 0 Write through Mode 1 Write back Mode CX bit 15 Size Information Valid Flag bits 14 0 Size of L2 Cache in 32KB blocks CF 1 AH 86h Function not supported NOTE T...

Page 73: ...e AMIBIOS ID version 3 format32 byte ID includes 3 7 byte board ID Pinot 1 byte board revision starting from 0 3 byte OEM ID 86B for standard BIOS 4 byte build number 1 3 byte describing build type D for development A for Alpha B for Beta Pxx for production version xx 6 byte build date in mmddyy format 4 byte build time in hhmm format 5 bytes reserved for future use CF 1 AH 86h Invalid parameters ...

Page 74: ... disabled via BIOS setup during POST the BIOS displays the usual POST screen including the memory count and processor information If Quiet Boot is enabled and a valid logo is detected the BIOS displays the logo during POST and suppresses the usual POST screen The user may press the ESC key to switch to the POST diagnostic screen from the logo The BIOS erases the logo when option ROMs are scanned b...

Page 75: ...ntry point exists for a given time during POST 3 The system state must be preserved by the User Binary 4 The user Binary code must be relocatable It will be located within the first Megabyte The User Binary code should not make any assumptions about the value of the code segment 5 The user Binary code will always be executed from RAM and never from flash The BIOS copies the User Binary into system...

Page 76: ...hat will be used if the Scan User Flash CU selection is enabled Use for Mandatory user binaries db 0CBh Signal to BIOS that what follows is a user binary that db 04h Bit map to define call points a one in any bit specifies that the BIOS will be called at that scan point in POST scan points to be defined jump table for each scan point JMP scanpoint_01h follows a list of 8 transfer JMP scanpoint_02h...

Page 77: ...the standard detection routines cannot handle the SMI 02h A stack is assured In addition the part of SMRAM that the User Binary is copied to can be used for storing data A User Binary implementation can reserve some bytes for data storage These locations can only be written to while in SMM Remember this is SMRAM and only accessible when in SMM It will persist between SMM invocations but not across...

Page 78: ...n about the system components The System Management BIOS Reference Specification and its companion DMTF Systems Standard Groups Definition define manageable attributes that are expected to be supported by SMBIOS enabled computer systems Many of these attributes have no standard interface to the management software but are known by the system BIOS The System Management BIOS Reference Specification ...

Page 79: ...Currently the power button in the SRMK2 does a request to the power state machine in the OSB4 It does not directly control power on the power supply 7 3 8 1 Going from Power Off to Power On The OSB4 monitors the power button and turns the system on When the OSB4 receives power good it performs a reset to put the system into an ON state The OSB4 may be configured to turn the system SRMK2 on for a v...

Page 80: ... capabilities of the system APIC information and bus structure The tables also describe control methods that operating system uses to change PCI interrupt routing enable disable devices in Super I O and find out the cause of the wake event ACPI Registers The constrained part of the hardware interface described at least in location by the ACPI Tables ACPI BIOS The code that boots the machine and im...

Page 81: ... the UDP Payload containing a 32 byte header followed by SMBIOS error data LAN alerts have the following structure struct header UINT8 signature 4 RCON UINT8 Version_no 1 UINT32 seq_no XXXX UINT32 ack_seq_no XXXX UINT8 command 0x4A UINT8 status X UINT16 data_size Total Data contained followed by the end of HEADER UINT8 reserved 0xF XXXXXXXXXXXXXXX typedef struct header HEADER See System Management...

Page 82: ...K2 supports paging as the result of a request from the ASM software Any POST error that gets logged in the SEL also causes a page out if paging is enabled If a page out is required the BIOS reads the Pager Number String in NVRAM and uses it to dial out this is set through the ASM software GSM paging is not supported on this platform and paging is turned off by default Paging is only supported thro...

Page 83: ... the System BIOS A new BIOS is contained in BIx files The number of BIx files is determined by the size of the BIOS area in the Flash part For further information on logical area 1 System BIOS see Table 4 1 Flash Table As of this writing the system BIOS area is 8 files 512KB They are named as follows XXXXXXXX BIO ß zero through XXXXXXXX BI7 The first 8 letters of each filename on the release diske...

Page 84: ...ng of certain hardware signals as documented in this section is followed This emulation is important to both OS and BIOS NMI handlers which have no knowledge of product specific errors but need to recover and shut down the system gracefully 9 2 Error Handlers The BIOS has an NMI handler that gets invoked when an NMI occurs in POST Generally the OS traps the NMI and does not pass it on to the BIOS ...

Page 85: ...essage and halt the system OS NMI Log the error and gracefully shut down the system BIOS SMI Log the event s Table 56 ISA bus error control bits Location Function Bit s Description Value I O 61h System Control 7 Memory parity check error flag RO 1 error 0 OK Port B 6 Channel check IOCHK error flag RO 5 4 Reserved 3 Channel check enable RW 1 enable 0 disable 2 Parity check enable RW system board er...

Page 86: ...ble SERR on Address Parity Error 1 enable 0 disable 3 Enable PERR on Received Data Parity Error 1 enable 0 disable 2 Enable SERR on ECC Uncorrectable Error 1 enable 0 disable 1 Enable SALERT on ECC Correctable Error 1 enable 0 disable 0 Enable SERR on Received Master Abort 1 enable 0 disable CNB30LE 47h ERRSTS 6 PCI Transmitted Data Parity Error 1 error 0 OK 5 PCI Received Data Parity Error 1 erro...

Page 87: ...its varies 9 3 4 System Limit Error The SRMK2 Heceta 3 ASIC monitors system operational limits It manages the A D converter defines voltage and temperature limits and defines chassis intrusion Any sensor values outside of specified limits are fully handled by the BIOS and OS software The BIOS response to any critical Heceta 3 error is to log the error display an error condition and shut down the s...

Page 88: ...powered by a battery The battery power is low Replace the battery CMOS Checksum Failure CMOS RAM checksum is different than the previous value Run WINBIOS Setup CMOS System Options Not Set The values stored in CMOS RAM have been destroyed Run WINBIOS Setup CMOS Display Type Mismatch The video type in CMOS RAM does not match the type detected Run WINBIOS Setup CMOS Memory Size Mismatch The amount o...

Page 89: ...blem Make sure a Keyboard Controller AMIBIOS is installed Set Keyboard in Advanced Setup to Not Installed to skip the keyboard POST routines KB Interface Error There is an error in the keyboard connector No ROM BASIC Cannot find a proper bootable sector on drive A C or CD ROM drive AMIBIOS cannot find ROM Basic Off Board Parity Error Parity error in memory installed on an adapter card in an expans...

Page 90: ...p Key Description Enter Select Submenu The Enter key activates sub menus when the selected feature is a sub menu displays a pick list if a selected feature has a value field or selects a sub field for multi valued features like time and date If a pick list is displayed the Enter key undoes the pick list and allows another selection in the parent menu ESC Exit The ESC key provides a mechanism for b...

Page 91: ...low Maintenance Main Advanced Security Boot System Management Exit Table 66 shows the Main menu This menu reports processor and memory information and is for configuring the system date and time Table 66 Main menu Feature Options Description System Time HH MM SS Sets the system time System Date MM DD YYYY Sets the system date Floppy A Not Installed 360 KB 5 1 2 MB 5 720 KB 3 1 44 1 25 MB 3 default...

Page 92: ...nced Security Boot System Management Exit Table 67 shows the Advanced menu This menu configures advanced features that are available through the chipset Table 67 Advanced menu Feature Options Description Peripheral Configuration See Table 68 Configures peripheral ports and devices Plug Play O S Yes No default Specifies if a Plug and Play operating system is being used No lets the BIOS configure al...

Page 93: ...ns Displays whether or not there is a supervisor password installed Default is no supervisor password installed Set Admin Password Press Enter to input a supervisor password Password can be up to seven alphanumeric characters Default is no supervisor password Set User Password Press Enter to input a user password Password can be up to seven alphanumeric characters Default is no user password User ...

Page 94: ...d IDE 4th IDE 2nd IDE default 3rd IDE default 4th IDE default Configures the peripheral devices Configurable options for other IDE devices are similar to Primary Master IDE Note that the Primary Master Slave IDE port is not available on the baseboard 1st to 6 th Boot Devices Floppy default IDE HDD ATAPI CD ROM ARMD FDD ARMD HDD Disabled Intel UNDI PXE 2 0 LAN 1 Intel UNDI PXE 2 0 LAN 2 AIC 7899 AI...

Page 95: ...for LAN console redirection and LAN alerts Event Log Configuration See Table 72 for Options Configures event log Note The LAN Console Redirection works with a client application This client application will be released on the support intel com website for the SRMK2 server Table 72 Event log configuration submenu Feature Options Description Event Log No options Displays whether or not there is spac...

Page 96: ... and loading default settings Table 73 Exit menu Feature Options Description Exit Saving Changes No options Exits system Setup and saves your changes in CMOS Exit Discarding Changes No options Exits system setup without saving your changes in CMOS Load Setup Defaults No options Loads setup defaults Load Custom Defaults No options Loads custom defaults Save Custom Defaults No options Save custom de...

Page 97: ...ss A Limit Radiated Conducted Emissions EN55024 Immunity Standard for Information Technology Equipment EN61000 3 2 Harmonic Currents EN61000 3 3 Voltage Flicker Australia New Zealand AS NZS 3548 Class A Limit Japan VCCI Class A ITE CISPR 22 Class A Limit IEC 1000 3 2 Harmonic Currents Taiwan BSMI Class A CISPR 22 Korea RRL Class A CISPR 22 Russia Gost Approval International CISPR 22 Class A Limit ...

Page 98: ...ction against harmful interference when the equipment is operating in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference In this case the user is ...

Page 99: ...eils numériques de Classe B prescrites dans la norme sur le matériel brouilleur Appareils Numériques NMB 003 édictée par le Ministre Canadian des Communications English translation of the notice above This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the interference causing equipment standard entitled Digital Apparatus ICES 003 o...

Page 100: ... to radio and TV reception All cables used to connect to peripherals must be shielded and grounded Operation with cables connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception NOTE If a Class A device is installed within this system then the system is to be considered a Class A system In this configuration operation of this equipment in a r...

Page 101: ...f 10 C per hour Non Operating Temperature 40 C to 70 C Non operating Humidity 95 non condensing 30 C Acoustic noise 6 8 Bel 8 Weighted Sound Power ISO 7779 Test Procedure Operating Shock No errors with a half sine wave shock of 2G with 11 millisecond duration Package Shock Operational after a 24 inch free fall although cosmetic damage may be present ESD 15kV per Intel Environmental test specificat...

Page 102: ... 55 800 000 39 278 hrs 12 2 Serviceability The desired Mean Time To Repair MTTR of the system is approximately less than 30 minutes including diagnosis of the system problem To meet this goal the system enclosure and hardware have been designed to minimize the MTTR Following are the maximum times that a trained field service technician should take to perform the listed system maintenance procedure...

Page 103: ...tion 103 13 Compatibility Testing At the time of this writing validation of the SRMK2 Internet Server with third party operating systems and hardware has not been completed Please visit http www intel com isp to find an up to date compatibility test report ...

Page 104: ... 3 Information Technology AT Attachment 3 Interface X3T10 2008D Revision 6 October 25 1995 ftp fission dt wdc com pub standards ATAPI ATA Packet Interface for CD ROMs SFF 8020i Revision 2 5 SFF Fax Access 408 741 1600 ATX ATX Form Factor Specification Revision 2 03 December 1998 Intel Corporation http www teleport com ffsupprt spec atxspecs htm BIOS Boot Specification BIOS Boot Specification BBS V...

Page 105: ...ation Intel Corporation Compaq Computer Corporation Dell Corporation Gateway Inc and Hewlett Packard Company http www microsoft com hwdev pc99 htm PCI PCI Local Bus Specification Revision 2 2 December 18 1998 PCI Special Interest Group Revision 1 1 December 18 1998 PCI Special Interest Group http www pcisig com Intel Pentium Pro BIOS Writer s Guide Intel Pentium Pro BIOS Writer s Guide Intel Corpo...

Page 106: ...ration IBM Corporation Phoenix Technologies Ltd and SystemSoft Corporation http developer intel com ial wfm design smbios SMSC FDC37B782 FDC37B78x PC98 99 Compliant Enhanced Super I O Controller with ACPI Support Real Time Clock and Consumer IR Standard Microsystems Corporation http www smsc com main datasheet html UHCI Universal Host Controller Interface UHCI Design Guide Revision 1 1 March 1996 ...

Page 107: ...ot GetServiceID GetAlertIP GetBootCount GetModemStr GetAlertMask GetLastState PutModemStr GetChecksum GetLastSensor GetPagerNum EnablePassword GetReasonCode PutPagerNum ChangePassword GetSerialConfig GetPagerStr DisablePassword ClearScreen After typing this command into the BIOS Console the display will clear ReadFRU This command will return the entire SMBIOS data structure which contains all FRU ...

Page 108: ...ssible values are 0 Unknown default 1 POST Machine is in POST 2 Emergency Mode BIOS emergency mode console redirection 3 OS Booting Bootstrap about to be loaded 4 OS Initializing OS booted and started running 5 OS Running OS fully up 6 OS Going Down OS starting graceful shut down 7 OS Down OS mostly shutdown All but essential processes and services GetLastSensor This code represents the last known...

Page 109: ... a value representing the COM port to be assigned to the serial or modem link 0 Disabled 1 COM1 2 COM2 3 COM3 default Rate is a value representing the speed of serial communication in bits per second 0 9600 bits second 1 19200 bits second default 2 38400 bits second 3 115200 bits second Flow is a value representing flow control 0 None 1 CTS RTS 2 XON XOFF 3 CTS RTS CD default Parity is a value rep...

Page 110: ...n next boot self clearing Bit 2 LAN Alerts Enable Bit 3 Paging Enable Bit 4 Console Redirection Enable Bit 5 Pager Control 1 page out on next boot self clearing Value is a decimal number The default is 16 GetServiceID This code is the partition ID that the BIOS will search for and boot to when going into service partition mode GetModemStr PutModemStr Initialization String Initialization String is ...

Page 111: ...be comprised of four 3 digit decimal values separated by periods This address should be in the same subnet as the management console since a default gateway is not stored GetStaticMask This is a string that represents the dotted IP subnet mask that should be used for the static IP address This string must be comprised of four 3 digit decimal values separated by periods GetAlertIP This is a string ...

Page 112: ...disable it Maximum password length is 20 characters and spaces are not allowed Help command Help This command will display the list of supported command with respective usage and a brief description BIOS Console input output formats The BIOS Console will prompt for input on the command line at the bottom of the display The command line will be displayed in reverse video It will then accept input f...

Page 113: ...0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00...

Page 114: ...ill not be echoed on the display as it is entered If the correct password is entered the standard prompt will be displayed and operation proceeds normally If an incorrect password is entered an error message is displayed followed by the password prompt Figure 29 Incorrect password Password Error Password ...

Page 115: ...Intel SRMK2 Internet Server Technical Product Specification 115 ...

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