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Intel® Server Platforms SR6850HW4 and SR6850HW4/M Product Guide
System Interconnection
BASEBOARD
PROCESSOR SOCKETS(4)
SMS
I/F
System LPC Bus
5V
12V
3.3V
-12V
Po
we
r Bu
tton
Fro
n
t Pane
l SDI S
w
itch
Thermal Trip
- Chassis ID
- Baseboard ID
- Power State
CPU Voltage
INTELLIGENT PLATFORM MANAGEMENT BUS (IPMB)
Res
et Button
Po
we
r Conne
c
tor
To Power
Distribution
Board
Baseboard
Temp 1
Pri
v
ate M
an
a
gement Bus
s
es
RAM
CODE
(updateable)
Non-volatile, read-write storage
SENSOR
DATA
RECORDS
SYSTEM
EVENT
LOG
FRU INFO
& CONFIG
DEFAULTS
SMM
I/F
CO
M 1
CO
M
M
MUX
BBD COM1
CPU FRU
CPU 'Core' Temp
FRU EEPROM
EMP
DIMM SPD (16)
CPU OEM NV
Power
L
E
D
Sy
s
tem Status
LE
D
FANs (6)
N
e
tw
o
rk
A
c
ti
vi
ty
LE
D
s
PCI PME
BASEBOARD
MANAGEMENT
CONTROLLER
(BMC)
System I/F
PORTS
1.25V
3.3V Standby
LVDS-B Term
LVDS-A Term
Dri
v
e
A
c
ti
vi
ty/Faul
t
L
E
D
Sy
s
te
m I
denti
fy
B
u
tt
o
n
Hot-swap
Backplane
Header
Aux. IPMB
Connector
Chip Set
ICMB
Transceiver
Header
Logic 2.5V
spkr
Identi
fy
L
E
D
Temp Sensor
DUAL
NIC
TCO
FRU EEPROM
Front Panel Connectors
Intel®
Management
Module
Figure 125. Interconnect Block Diagram