C. System Registers
72
Watchdog (79h), continued
Bit Description
5
Stage 2 Enable
Enables second stage (Reset) activation on timeout.
Read Value:
0 = Reset activation on timeout disabled.
1 = Reset activation on timeout enabled.
Write Value:
0 = Reset operation of the watchdog is not enabled. When the watchdog times out,
the
Stage 2 Monitor bit
is not set to 1 and the Reset output is not asserted.
1 = Reset operation of the watchdog is enabled. When and if the watchdog times
out:
•
The Reset output asserts.
•
The
Stage 2 Monitor bit
is set to 1 and stays high until set to 0 by software.
•
Reset action occurs approximately 250 ms after the NMI or INIT action.
Power Up Value = 0.
Value After Timeout = 0 (doesn't re-arm).
A hard reset will set this bit to 0.
4
Stage 1 Enable
Enables NMI or INIT activation on timeout.
Read Value:
0 = Disabled.
1 = Enable NMI activation on timeout if
bit 3
= 0.
Enable INIT activation on timeout if bit 3 = 1.
Write Value:
0 = Disable NMI operation of the watchdog. When the watchdog times out, the
Stage 1 Monitor bit
is not set to 1 and the NMI or INIT output is not asserted.
1 = Enable NMI operation of the watchdog. When and if the watchdog times out:
•
The Stage 1 output (NMI if
bit 3
= 0 or INIT if bit 3 = 1) occurs after the period of time
specified by the
Terminal Count bits
.
•
The
Stage 1 Monitor bit
is set to 1 and stays high until set to 0 by software.
•
The Stage 2 Reset occurs approximately 250 ms after Stage 1 output, allowing the
system software to take action before the reset occurs.
Power Up Value = 0.
Post Timeout Value = 0.
A hard reset will set this bit to 0.
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