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7. Watchdog Timer
This chapter explains the operation of the ZT 5504's watchdog timer. It provides an overview of
watchdog operation and features, as well as sample code to help you learn how the watchdog
timer works with applications.
Watchdog Timer Overview
The primary function of the watchdog timer is to monitor the ZT 5504's operation and take
corrective action if the software fails to function as programmed. The major features of the
watchdog timer are:
•
Two-stage operation
•
Enabled and disabled through software control
•
Armed and strobed through software control
Watchdog Timer Architecture
Address/Data
Port 79h
Control
and Status
Register
Slow Clock
Counter
Watchdog Circuit
Reset
NMI
CPU Init
The ZT 5504's custom watchdog timer circuit is implemented in a programmable logic device.
The watchdog timer contains a "Control and Status Register" which is documented in
Appendix C as
Watchdog (79h)
. The register allows applications to determine if a watchdog
timeout caused a particular reset.
The watchdog timer drives the First and Second Stages as follows:
1. The watchdog times out (First Stage) after a selected timeout interval.
2. NMI or INIT (software selectable) is driven high.
3. A hard reset occurs (Second Stage) 250 ms later.
Eight timeout intervals are selectable through bits 0-2 of the register. The intervals range from a
minimum of 250 ms to a maximum of 256 seconds.
The watchdog is normally strobed by reading the Watchdog Register (79h), which clears the
counter. Writes to this register also clear the counter.
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