7. Watchdog Timer
47
Power Up Initialization
The watchdog timer's logic is initialized at power up. This ensures that the STAGE1 MONITOR,
STAGE2 MONITOR, STAGE1 ENABLE, and STAGE2 ENABLE status and control bits power
up to unasserted states (0). This allows an application to determine if the reset was caused by
a watchdog timeout or a power up.
Timeout Values
The watchdog timer has a separate slow clock source that runs at a maximum frequency of
32 Hz (25 Hz nominal). Because the clock is based on an RC oscillator, the nominal timeout
period is approximately 30% longer than the minimum value. The watchdog is guaranteed to
timeout in no less than the programmed minimum value.
Using the Watchdog in an Application
The following topics are provided to aid you in learning to use watchdog in an application. The
watchdog's Reset and NMI functions are described and sample code is provided.
Watchdog Reset and NMI are controlled through the watchdog's "Control and Status Register",
documented in Appendix C as
Watchdog (79h)
.
Watchdog Reset
An application using the reset feature enables the watchdog reset, sets the terminal count
period, and then periodically strobes the watchdog to keep it from resetting the system. If a
strobe is missed, the watchdog times out and resets the system hardware.
Enabling the Watchdog Reset
C code for enabling the watchdog reset might look like the following:
#define WD_RESET_EN_BIT_SET
0x20
void EnableWatchdogReset(void){
unsigned char WdValue;
// Holds watchdog register values.
//
WdValue = inb(WD_CSR_IO_ADDRESS);
// Read the current contents of the
// watchdog register.
WdValue |= WD_RESET_EN_BIT_SET;
// Assert the enable bit in the
// local copy.
outb(WD_CSR_IO_ADDRESS,WdValue);
// Assert the enable in the
// watchdog register.
}
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