INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
42
Workaround:
All bus agents that support system bus ECC must disable it when a 2:1 ratio is used.
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
C35.
Fault on REP CMPS/SCAS Operation May Cause Incorrect
EIP
Problem:
If either a General Protection Fault, Alignment Check Fault or Machine Check Exception occur
during the first iteration of a REP CMPS or a REP SCAS instruction, an incorrect EIP may be pushed onto the
stack of the event handler if all the following conditions are true:
•
The event occurs on the initial load performed by the instruction(s)
•
The condition of the zero flag before the repeat instruction happens to be opposite of the repeat condition
(i.e., REP/REPE/REPZ CMPS/SCAS with ZF = 0 or RENE/REPNZ CMPS/SCAS with ZF = 1)
•
The faulting micro-op and a particular micro-op of the REP instruction are retired in the retirement unit in
a specific sequence
The EIP will point to the instruction following the REP CMPS/SCAS instead of pointing to the faulting
instruction.
Implication:
The result of the incorrect EIP may range from no effect to unexpected application/OS
behavior.
Workaround:
None identified
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
C36.
RDMSR or WRMSR To Invalid MSR Address May Not Cause
GP Fault
Problem:
The RDMSR and WRMSR instructions allow reading or writing of MSRs (Model Specific
Registers) based on the index number placed in ECX. The processor should reject access to any reserved or
unimplemented MSRs by generating #GP(0). However, there are some invalid MSR addresses for which the
processor will not generate #GP(0).
Implication:
For RDMSR, undefined values will be read into EDX:EAX. For WRMSR, undefined processor
behavior may result.
Workaround:
Do not use invalid MSR addresses with RDMSR or WRMSR.
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
