INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
13
Summary of Errata
NO. CPUID/Stepping Plans
ERRATA
650h
A0
651h
A1
660h
A0
665h
B0
683h
B0
686h
C0
68Ah
D0
6B1h
A1
6B4h
B1
cache line replacement
C11
X
X
X
X
Fixed
Potential early deassertion of
LOCK# during split-lock
cycles
C12
X
X
X
X
Fixed
A20M# may be inverted after
returning from and Reset
SMM
C13 X X
Fixed
Reporting
of
floating-point
exception may be delayed
C14
X
X
X
X
X
X
X
X
X
NoFix
Near CALL to ESP creates
unexpected EIP address
C15
X
X
Fixed
Built-in self test always gives
nonzero result
C16
X
X
X
X
Fixed
THERMTRIP# may not be
asserted as specified
C17
X
Fixed
Cache state corruption in the
presence of page A/D-bit
setting and snoop traffic
C18 X
Fixed
Snoop
cycle
generates
spurious machine check
exception
C19 X X
Fixed
MOVD/MOVQ
instruction
writes to memory
prematurely
C20
X
X
X
X
X
X
X
X
X
NoFix
Memory type undefined for
nonmemory operations
C21
X
X
Fixed
Bus protocol conflict with
optimized chipsets
C22 X X X X X X X X X NoFix
FP
Data
Operand
Pointer
may not be zero after power
on or Reset
C23 X X X X X X X X X NoFix
MOVD
following
zeroing
instruction can cause
incorrect result
C24 X X X X X X X X X NoFix
Premature
execution
of
a
load operation prior to
exception handler invocation
C25 X X X X X X X X X NoFix
Read
portion
of
RMW
instruction may execute
twice
