Intel CELERON 1.10 GHZ Specification Download Page 91

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INTEL

CELERON® PROCESSOR SPECIFICATION UPDATE

The

Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference

Appendix A, Table A-2,

the opcode corresponding to 0x33 currently states:

Gb, Ev

It should state:

Gv, Ev

Also, Page 3-791, XOR-Logical Exclusive OR, the two entries for opcode 33 currently state:

Opcode

Instruction

Description

33 /r

XOR r16,r/m16

r8 XOR r/m8

33 /r

XOR r32,r/m32

r8 XOR r/m8

It should state

Opcode

Instruction

Description

33 /r

r16 XOR r/m16

r8 XOR r/m8

33 /r

r32 XOR r/m32

r8 XOR r/m8

C10.

Incorrect Information for SLDT

In the

Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference,

the

opcode/Instruction/Description table for SLDT currently states “SLDT

r/m32

Store segment selector from

LDTR in low-order 16 bits of

r/m32

” but should instead list “SLDT

r32

Store segment selector from LDTR in

low-order 16 bits of

r32

.”

In the

Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference,

the sentence in the

LGDT/LIDT instruction section currently states:

”See 'SFENCE -- Store Fence' in this chapter for information on storing the contents of the GDTR
and IDTR."

It should state:

"See 'SGDT/SIDT' in this chapter for information on storing the contents of the GDTR and IDTR."

C9.

0x33 Opcode

C11. LGDT/LIDT Instruction Information Correction

Summary of Contents for CELERON 1.10 GHZ

Page 1: ...gust 2007 Document Number 243748 051 The Intel Celeron processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current chara...

Page 2: ...without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no resp...

Page 3: ...eron Processor and Boxed Intel Celeron Processor Markings PPGA Package 2 Intel Celeron Processor and Boxed Intel Celeron Processor Markings FC PGA FC PGA2 Package 3 IDENTIFICATION INFORMATION 4 SUMMAR...

Page 4: ...re Updated Errata C1 and C27 Added Errata C37 through C39 Added Specification Clarification C15 Added Specification Change C2 November 1998 008 Updated Erratum C23 Added Erratum C40 Updated Documentat...

Page 5: ...Summary of Documentation Changes Summary of Specification Clarifications and Summary of Changes tables Added Specification Change C2 June 2000 025 Added Specification Change C3 July 2000 026 Added Er...

Page 6: ...Table January 2002 040 Updated Processor Identification Information Table January 2002 041 Added the 1A and 1 10A GHz specifications February 2002 042 Added the 566 MHz at 1 75 VID specifications Marc...

Page 7: ...INTEL CELERON PROCESSOR SPECIFICATION UPDATE v REVISION HISTORY Date of Revision Version Description August 2007 051 Updated Summary Table of Changes Added Erratum C111...

Page 8: ...ed L2 cache size package type etc as described in the processor identification information table Care should be taken to read all notes associated with each S Spec number Errata are design defects or...

Page 9: ...ATION Intel Celeron Processor and Boxed Intel Celeron Processor Markings S E P Package i m 98 celeron Static White Silkscreen marks 266 66 COA FFFFFFFF SYYYY Dynamic laser mark area NOTES SYYYY S spec...

Page 10: ...onTM AAAAAAAZZZ LLL SYYYY Country of Origin FFFFFFFF XXXX M C 98 i Top Bottom e int l NOTES AAAAAAA Product Code ZZZ Processor Speed MHz LLL Integrated Level Two Cache Size in Kilobytes SYYYY S Spec N...

Page 11: ...PGA2 Package FC PGA 370 Pin Package GRP1LN1 INTEL m c 01_ _ COO GRP1LN2 Core Freq Cache Bus Freq Voltage GRP2LN1 FPO S N GRP2LN2 CELERON S Spec FC PGA2 370 Pin Package GRP2LN1 GRP2LN2 GRP1LN1 GRP1LN2...

Page 12: ...nature of 0x6B1 The Celeron processor s second level L2 cache size can be determined by the following register contents 0 Kbyte Unified L2 Cache 1 40h 128 Kbyte Unified L2 Cache 1 41h 256 Kbyte 8 way...

Page 13: ...v 1 1 SL2Y4 B0 0 0652h 300 66 SEPP Rev 1 1 SL2WM A0 128 0660h 300A 66 SEPP Rev 1 3 SL32A A0 128 0660h 300A 66 SEPP Rev 1 1 SL2WN A0 128 0660h 333 66 SEPP Rev 1 3 SL32B A0 128 0660h 333 66 SEPP Rev 1 1...

Page 14: ...66 PPGA 2 SL46S B0 128 0683h 533A 66 FC PGA SL3W6 B0 128 0683h 533A 66 FC PGA 2 SL46T B0 128 0683h 566 66 FC PGA SL3W7 B0 128 0683h 566 66 FC PGA 2 SL4PC C0 128 0686h 566 66 FC PGA 2 7 5 SL4NW C0 128...

Page 15: ...PGA 2 4 5 SL52X D0 128 068Ah 766 66 FC PGA 4 8 SL5EA D0 128 068Ah 766 66 FC PGA 2 4 8 SL4TF C0 128 0686h 800 100 FC PGA 4 5 SL45R C0 128 0686h 800 100 FC PGA 2 4 5 SL54P D0 128 068Ah 800 100 FC PGA 4...

Page 16: ...CESSOR SPECIFICATION UPDATE 8 Intel Celeron Processor Identification Information S Spec Core Stepping L2 Cache Size Kbytes CPUID Speed MHz Core Bus Package and Revision Notes SL634 D0 128 068Ah 950 10...

Page 17: ...SL6CA B1 256 06B4h 1 10A GHz 100 FC PGA2 13 15 SL6JR B1 256 06B4h 1 10A GHz 100 FC PGA2 2 13 15 SL5XS A1 256 06B1h 1 20 GHz 100 FC PGA2 12 13 SL5Y5 A1 256 06B1h 1 20 GHz 100 FC PGA2 2 12 13 SL656 A1...

Page 18: ...an heatsink 3 This part also ships as a boxed Celeron processor with an attached fan heatsink 4 This part requires Tj of 80 C 5 This part uses a VCCCORE of 1 7 V 6 This part will require Tj of 82C 7 T...

Page 19: ...is prefixed with a capital letter to distinguish the product The key below details the letters that are used in Intel s microprocessor Specification Updates A Dual Core Intel Xeon processor 7000 seque...

Page 20: ...R Intel Celeron processor 500 series AS Intel Xeon processor 7200 7300 series Summary of Errata NO CPUID Stepping Plans ERRATA 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 C...

Page 21: ...HERMTRIP may not be asserted as specified C17 X Fixed Cache state corruption in the presence of page A D bit setting and snoop traffic C18 X Fixed Snoop cycle generates spurious machine check exceptio...

Page 22: ...ng C31 X X Fixed Incorrect memory type may be used when MTRRs are disabled C32 X X X Fixed Misprediction in program flow may cause unexpected instruction execution C33 X X X X X X X X X NoFix Data Bre...

Page 23: ...ROB_CR_BKUPTMPDR6 C45 X X X X X Fixed Machine Check Exception may occur due to improper line eviction in the IFU C46 X X X X X X X X X NoFix Lower bits of SMRAM SMBASE register cannot be written with...

Page 24: ...roblematic in MP systems C58 X X X X X NoFix INT 1 with DR7 GD set does not clear DR7 GD C59 X X X X X NoFix Potential loss of data coherency during MP data ownership transfer C60 X X X X X NoFix Misa...

Page 25: ...cause processor deadlock C74 X X X X X X X X X NoFix Processor may report invalid TSS fault instead of Double fault during mode C paging C75 X X Fixed APIC failure at CPU core system bus frequency of...

Page 26: ...ng into a Page with a Different Memory Type C87 X X X X X X X X X NoFix POPF and POPFD Instructions that Set the Trap Flag Bit May Cause Unpredictable Processor Behavior C88 X X X X X X X X X NoFix Th...

Page 27: ...ithout an Intervening FP Floating Point Instruction May Save Uninitialized Values for FDP x87 FPU Instruction Operand Data Pointer Offset and FDS x87 FPU Instruction Operand Data Pointer Selector C96...

Page 28: ...Memory Types may use an Incorrect Data Size or Lead to Memory Ordering Violations C105 X X X X X X X X X NoFix The BS Flag in DR6 May be Set for Non Single Step DB Exception C106 X X X X X X X X X NoF...

Page 29: ...Doc EFLAGS Register Correction C8 X X X X X X X X X Doc PSE 36 Paging Mechanism C9 X X X X X X X X X Doc 0x33 Opcode C10 X X X X X X X X X Doc Incorrect Information for SLDT C11 X X X X X X X X X Doc...

Page 30: ...es CPUID Stepping NO 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 Plans DOCUMENTATION CHANGES C22 X X X X X X X X X Doc Cache Description C23 X X X X X X X X X Doc Instructi...

Page 31: ...A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 Plans SPECIFICATION CLARIFICATIONS C1 X X X X X X X X X Doc PWRGOOD inactive pulse width C2 X X X X X X X X X Doc Floating point opcode clarification...

Page 32: ...ID Stepping NO 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 Plans SPECIFICATION CHANGES C1 X X X X X X X X X Doc RESET pin definition C2 X X X Doc Tco max revision for 533A...

Page 33: ...currently identified any software which exhibits this behavior Workaround If the FP Data Operand Pointer is used in an OS which may run 16 bit floating point code care must be taken to ensure that no...

Page 34: ...eakpoints will avoid the first three cases of this erratum No workaround has been identified for cases 4 or 5 Status For the steppings affected see the Summary of Changes at the beginning of this sect...

Page 35: ...happens frequently and produces a rounded result acceptable to most applications The PE bit of the FPU status word may not always be set upon receiving an inexact result exception Thus if these excep...

Page 36: ...f there is not the SMM handler may proceed with its normal operation Status For the steppings affected see the Summary of Changes at the beginning of this section C7 Branch Traps Do Not Function If BT...

Page 37: ...ormation The value of LBER should be used with caution when debugging branching code if the values in the LBR and LBER are the same then the LBER value is incorrect Also the value in the LBER should n...

Page 38: ...to occur 1 The assertion of A20M in real address mode 2 After entering the 1 Mbyte address wrap around mode caused by the assertion of A20M there is an assertion of SMI intended to cause a Reset or re...

Page 39: ...truction and the MOVQ or MOVD instruction will give the expected results This is already the recommended practice for software Status For the steppings affected see the Summary of Changes at the begin...

Page 40: ...onal on the Celeron processor Note that this erratum can only occur when the processor is running with a TPLATE temperature over the maximum specification of 75 C Workaround Avoid operation of the Cel...

Page 41: ...asked floating point exception 4 If CR0 TS 1 Task Switched bit then the store could happen prior to the triggered Device Not Available DNA exception If the MOVD MOVQ instruction is restarted after han...

Page 42: ...g of this section C20 Memory Type Undefined for Nonmemory Operations Problem The Memory Type field for nonmemory transactions such as I O and Special Cycles are undefined Although the Memory Type attr...

Page 43: ...Pointer may be nonzero after power on or Reset Implication Software which uses the FP Data Operand Pointer and count on its value being zero after power on or Reset without first executing an FINIT F...

Page 44: ...16 1024 and that any value in the range for the size may be affected Also note that this erratum may occur with EAX replaced with any 32 bit general purpose register and AX with the corresponding 16...

Page 45: ...n or MMX instruction that performs a memory load has a floating point exception pending 3 If an MMX instruction that performs a memory load and has either CR0 EM 1 Emulation bit set or a floating poin...

Page 46: ...will cause the processor to enter an invalid test state Implication If this erratum occurs the system may boot normally however L2 cache may not be initialized Workaround Ensure that the 2 5 V VCC2 5...

Page 47: ...ges at the beginning of this section C29 MOV With Debug Register Causes Debug Exception Problem When in V86 mode if a MOV instruction is executed on debug registers a general protection exception GP s...

Page 48: ...aching and the Page Attribute Table PAT entries are left in their default setting which includes UC memory type PCD 1 PWT 0 see the Intel Architecture Software Developer s Manual Volume 3 System Progr...

Page 49: ...e Summary of Changes at the beginning of this section C33 Data Breakpoint Exception in a Displacement Relative Near Call May Corrupt EIP Problem If a misaligned data breakpoint is programmed to the sa...

Page 50: ...REP instruction are retired in the retirement unit in a specific sequence The EIP will point to the instruction following the REP CMPS SCAS instead of pointing to the faulting instruction Implication...

Page 51: ...will also exhibit this behavior for both CS and SS when executed with the value in SYSENTER_CS_MSR between FFF0h and FFF3h or between FFE8h and FFEBh Implication These instructions are intended for o...

Page 52: ...as discovered in a focused testing environment Workaround Ensure that OS code does not clear the D bit for system pages including any pages that contain a task gate or TSS Use task gates rather than j...

Page 53: ...write This presents a small window of opportunity for a fast bus mastering I O device which triggers an action based on the second UC write to arbitrate and gain ownership of the bus prior to the comp...

Page 54: ...em bus At the same time a locked access to the L1 cache occurs Implication A Celeron processor may cause a system to hang if the above listed sequence of events occur The probability of encountering t...

Page 55: ...tems as they do not have multi processor support If this erratum does occur a machine check exception will result Note systems that implement an operating system that does not enable the Machine Check...

Page 56: ...g system may alternately use software task management Status For the steppings affected see the Summary of Changes at the beginning of this section C48 Cross Modifying Code Operations on a Jump Instru...

Page 57: ...ssemblers do not generate this type of code sequence and will normally flag such a sequence as an error If this erratum occurs the processor deadlock condition will occur and result in a system hang C...

Page 58: ...software applications Workaround None identified Status For the stepping affected see the Summary of Changes at the beginning of this section C52 Cache Line Reads May Result in Eviction of Invalid Dat...

Page 59: ...hould take care to execute a WBINVD instruction before the AP is taken off line using an INIT_IPI Status For the steppings affected see the Summary of Changes at the beginning of this section C54 Doub...

Page 60: ...DTLB by speculative loads from other instructions that hit the same way of the DTLB before the store has completed DTLB eviction requires at least three load operations that have linear address bits...

Page 61: ...software which exhibits this problem Workaround Follow a homogenous model for the memory type range registers MTRRs ensuring that all processors have the same cacheability attributes for each region o...

Page 62: ...also unaffected This erratum does not affect uniprocessor systems The existence of this erratum was discovered during ongoing design reviews but it has not as yet been reproduced in a lab environment...

Page 63: ...xecute and retire placing the instruction pointer back to instruction 7 This is due to the condition at the end of the wait0 loop being false The livelock scenario can occur if the timing of the wait0...

Page 64: ...ed have been evicted from the IFU The one cycle long window is opened when an opportunistic fetch receives a partial hit on a previously executed but not as yet completed store resident in the store b...

Page 65: ...ster has been zeroed with either a SUB reg reg instruction or an XOR reg reg instruction 2 A value is moved with sign extension into the same register s lower 16 bits or a signed integer multiply is p...

Page 66: ...uce the correct answer If AX is negative bit 15 of AX is 1 MOVD or CVTSI2SS may produce the right answer or the wrong answer depending on the point in time when the MOVD or CVTSI2SS instruction is exe...

Page 67: ...not suppress snoop traffic before the assertion of the FLUSH pin may cause a line to be left in an incorrect cache state Workaround Affected systems those capable of asserting the FLUSH pin should pre...

Page 68: ...IT may not flush a TLB entry when 1 The processor is in protected mode with paging enabled and the page global enable flag is set PGE bit of CR4 register 2 G bit for the page table entry is set 3 TLB...

Page 69: ...id then the new PDPTR will not be loaded This will lead to the reporting of invalid TSS fault instead of the expected Double fault Implication Operating systems that access an invalid TSS may get inva...

Page 70: ...e Problem At the beginning of the IRET instruction execution in VM86 mode the lower 16 bits of the ESP register are saved as the old stack value When a fault occurs these 16 bits are moved into the 32...

Page 71: ...nges at the beginning of this section C80 The Processor Might not Exit Sleep State Properly Upon De assertion of CPUSLP Signal Problem If the processor enters a sleep state upon assertion of CPUSLP si...

Page 72: ...e TCK signal during the power on sequence that meets all of the following requirements Rising edge occurs after Vcc_core is valid and stable Rising edge occurs before or at the de assertion of RESET R...

Page 73: ...1 3K ohm TCK PGA370 ITP 2 5V For Production Boards Depopulate R5 To use ITP Install R5 Depopulate R4 The example workaround circuit assumes that the PWRGD inputs into the processors are open collecto...

Page 74: ...x6BX The intervening micro instructions must not have any events or faults When the instruction from event 2 retires the StallMS condition within the event 5 instruction fails to operate correctly and...

Page 75: ...when the string operation crosses a page boundary into an Uncacheable UC memory type Also if the fast string operation crosses a page boundary into a WC memory region the processor will not self snoo...

Page 76: ...POPF and POPFD Instructions that Set the Trap Flag Bit May Cause Unpredictable Processor Behavior Problem In some rare cases POPF and POPFD instructions that set the Trap Flag TF bit in the EFLAGS reg...

Page 77: ...FST instruction the processor reports a numeric exception instead of reporting an exception because of a Null segment If the numeric exception handler tries to access the FST data it will get a GP fau...

Page 78: ...es of Changes C93 Under Certain Conditions LTR Load Task Register Instruction May Result in System Hang Problem An LTR instruction may result in a system hang if all the following conditions are met 1...

Page 79: ...uction may save uninitialized values for the FPUDataPointer Implication When this erratum occurs the values for FPUDataPointer in the saved floating point image or floating point environment structure...

Page 80: ...Pending May Cause an Unexpected Interrupt Problem If a local interrupt is pending when the LVT entry is written an interrupt may be taken on the new interrupt vector even if the mask bit is set Impli...

Page 81: ...take effect before the actual priority has been lowered This may cause interrupts whose priority is lower than the initial TPR but higher than the final TPR to not be serviced until the interrupt ena...

Page 82: ...ode the CPU will incorrectly update the LBR Last Branch Record and the BTS Branch Trace Store hence rendering their data invalid The corresponding data if sent out as a BTM on the system bus will also...

Page 83: ...memory types may start using an incorrect data size or may observe memory ordering violations Implication Upon crossing the page boundary the following may occur dependent on the new page memory type...

Page 84: ...refer to Procedure Calls For Block Structured Languages in IA 32 Intel Architecture Software Developer s Manual Vol 1 Basic Architecture for information on the usage of the ENTER instructions This er...

Page 85: ...gnaling a Code Segment Limit Fault Problem If code segment limit is set close to the end of a code page then due to this erratum the memory page Access bit A bit may be set for the subsequent page pri...

Page 86: ...s including EMMS are executed immediately after the last FP instruction an FP to MMX transition may not be counted Implication The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may...

Page 87: ...E6 The third opcode byte of these three byte opcodes should not be thought of as a prefix even though it has the same encoding as the operand size prefix 66H or one of the repeat prefixes F2H and F3H...

Page 88: ...CKSSWB DW PACKUSWB PADDB W D PADDSB W PADDUSB W PAND PANDN PCMPEQB W D PCMPGTB W D PMADDWD PMULHW PMULLW POR PSLLW D Q PSRAW D PSRLW D Q PSUBB W D PSUBSB W PSUBUSB W PUNPCKHBW WD DQ PUNPCKLBW WD DQ PX...

Page 89: ...tric domain for C2 is incorrect Under the FPU Flags affected C2 currently states C2 Set to 1 if source operand is outside the range 2 63 to 2 63 otherwise cleared to 0 It should state C2 Set to 1 if o...

Page 90: ...egister CR4 Set to 1 to enable the page size extension for 4 Mbyte pages PAE flag bit 5 in control register CR4 Clear to 0 to disable the PAE paging mechanism It should state As is shown in Table 3 3...

Page 91: ...SLDT In the Intel Architecture Software Developer s Manual Vol 2 Instruction Set Reference the opcode Instruction Description table for SLDT currently states SLDT r m32 Store segment selector from LDT...

Page 92: ...1 xmm2 m128 2 Page A 9 Table A 3 Two byte Opcode Map 08H 7FH First Byte is 0FH entry 2B currently states MOVNTPS Wps Vps MOVNTPS 66 Wpd Vpd It should state MOVNTPS Wps Vps MOVNTPD 66 Wpd Vpd 3 Page A...

Page 93: ...able A 3 Two byte Opcode Map 88H 7FH First Byte is FFH It should state Table A 3 Two byte Opcode Map 88H 7FH First Byte is 0FH 7 Page A 11 Table A 3 Two byte Opcode Map 88H 7FH First Byte is 0FH Entry...

Page 94: ...d state PMULLW Packed multiplication store low word 12 Page B 40 Table B 19 Formats and Encodings of the SSE2 SIMD Integer Instruction Entry PMADD currently states PMADD Packed multiply add It should...

Page 95: ...rchitecture Section 5 8 INSTRUCTION SET SUMMARY currently states RSM Return from system management mode SSM It should state RSM Return from system management mode SMM The Intel Architecture Software D...

Page 96: ...AF 1 THEN AL AL 6 CF CF OR CarryFromLastAddition CF OR carry from AL AL 6 AF 1 ELSE AF 0 FI IF AL AND F0H 90H or CF 1 THEN AL AL 60H CF 1 ELSE CF 0 FI It should state Operation old_AL AL old_CF CF CF...

Page 97: ...OR AF 1 THEN AL AL 6 CF CF OR CarryFromLastAddition CF OR carry from AL AL 6 AF 1 ELSE AF 0 FI IF AL 9FH or CF 1 THEN AL AL 60H CF 1 ELSE CF 0 FI It should state Operation old_AL AL old_CF CF CF 0 IF...

Page 98: ...debug exception handler the handler must set the LBR flag again to re enable last branch recording It should state 15 5 3 Monitoring Branches Exceptions and Interrupts Pentium 4 and Intel Xeon Proces...

Page 99: ...he CPL is greater than the current IOPL The Intel Architecture Software Developer s Manual Vol 2 Instruction Set Reference Section 3 2 Instruction Reference under MAXSS Return Maximum Scalar Single Pr...

Page 100: ...er s Manual Vol 1 Basic Architecture Chapter 12 section 12 5 2 on Figure 12 2 I O Permission Bit Map currently states Last byte of bit map must be followed by a byte with all bits It should state Last...

Page 101: ...Programming Guide section 14 5 currently states 14 5 MACHINE CHECK INITIALIZATION To use the processors machine check architecture software must initialize the processor to activate the machine check...

Page 102: ...BANK_NUMBER DO IA32_MCi_STATUS 0000000000000000H clears all errors OD FI Set the MCE flag bit 6 in CR4 register to enable machine check exceptions FI It should state 14 5 MACHINE CHECK INITIALIZATION...

Page 103: ...r of error reporting banks supported COUNT IA32_MCG_CAP Count MAX_BANK_NUMBER COUNT 1 IF Processor Family is 6H THEN Enable logging of all errors except for MC0_CTL register FOR error reporting banks...

Page 104: ...IA32_MCi_STATUS 0 OD ELSE FOR error reporting banks 0 through MAX_BANK_NUMBER DO Optional for BIOS and OS Log valid errors OS only IA32_MCi_STATUS 0 OD FI FI FI Setup the Machine Check Exception MC ha...

Page 105: ...ch Intel Architecture instruction For some instructions the clarification phrase below needs to either be added to their existing Comments section or a Comments section needs to be created with the cl...

Page 106: ...tem Programming Guide The MTRRs must be disabled prior to initialization or modification C4 Non AGTL Output Low Current Clarification In Table 6 of the Intel Celeron Processor Datasheet the note in bo...

Page 107: ...ctive for at least one millisecond after VCCCORE and CLK have reached their proper specifications They should state For a Power on or warm reset RESET must stay active for at least one millisecond aft...

Page 108: ...3 and column 4 Processor Power and Processor Core Power from Table 37 of the Intel Celeron Processor Datasheet Additional derating of the thermal design power and design requirements will result in a...

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