INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
74
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a linear address has bit 20 set
•
the address references a large page
•
A20M# is enabled
Implication:
When A20M# is enabled and an address references a large page the resulting
translated physical address may be incorrect. This erratum has not been
observed with any commercially available operating system.
Workaround:
Operating systems should not allow A20M# to be enabled if the masking of
address bit 20 could be applied to an address that references a large
page. A20M# is normally only used with the first megabyte of memory.
Status:
For the steppings affected, see the Summary Tables of Changes.
C102.
Values for LBR/BTS/BTM will be Incorrect after an Exit from
SMM
Problem:
After a return from SMM (System Management Mode), the CPU will incorrectly
update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence
rendering their data invalid. The corresponding data if sent out as a BTM on the
system bus will also be incorrect.
Note: This issue would only occur when one of the 3 above mentioned debug support facilities are used.
Implication:
The value of the LBR, BTS, and BTM immediately after an RSM operation
should not be used.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
C103 INIT Does Not Clear Global Entries in the TLB
Problem:
INIT may not flush a TLB entry when:
1. The processor is in protected mode with paging enabled and the page global
enable flag is set (PGE bit of CR4 register)
2. G bit for the page table entry is set
3. TLB entry is present in TLB when INIT occurs.
Implication:
Software may encounter unexpected page fault or incorrect address translation
due to a TLB entry erroneously left in TLB after INIT.
