INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
97
SPECIFICATION CLARIFICATIONS
The Specification Clarifications listed in this section apply to the following documents:
•
Pentium
®
II
Processor Developer’s Manual
•
P6 Family of Processors Hardware Developer's Manual
•
Intel
®
Celeron
®
Processor
Datasheet
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual
,
Volumes 1, 2A, 2B, 3A and 3B.
All Specification Clarifications will be incorporated into a future version of the appropriate Celeron
processor
documentation.
C1.
PWRGOOD Inactive Pulse Width
In Table 16 of the
Intel
®
Celeron
®
Processor Datasheet
, footnote 9 should read as follows:
9.
When driven inactive or after V
CCCORE
, V
CCL2
, and BCLK become stable. PWRGOOD must remain
below VIL,max from Table 8 until all the voltage planes meet the voltage tolerance specifications in Table
6 and BCLK has met the BCLK AC specifications in Table 11 for at least 10 clock cycles. PWRGOOD
must rise glitch-free and monotonically to 2.5 V.
C2.
Floating-Point Opcode Clarification
Section 3.2 of the
Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference,
provides detailed descriptions of each Intel Architecture instruction. For some instructions, the clarification
phrase below needs to either be added to their existing “Comments” section or a “Comments” section needs
to be created with the clarification phrase. The phrase is as follows:
The (
Instruction
shown in the center column of the table below) instruction is actually a
combination of two instructions - the FWAIT instruction followed by (
Instruction
shown in the
table). If the (
Instruction
shown in the table) instruction should fault in some way (e.g., page
fault), the value of EIP that is passed to the fault handler will be equal to the EIP of the first
instruction plus one (i.e., the EIP of the second of the pair of instructions). The FWAIT portion
of the combined instruction will have completed execution and will typically not be, nor need to
be, re-executed after the fault handler is completed.
The following table lists the affected instructions and the location of the clarification phrase:
Instruction Set Reference
Section Opcode
Instruction
Addition
Addition
to Page
FCLEX/FNCLEX-Clear
Exceptions
9B DB E2
FCLEX
Add “Comments”
section with
clarification phrase
3-177
FINIT/FNINIT-Initialize
Floating-Point Unit
9B DB E3
FINIT
Add clarification
phrase to existing
“Comments”
section
3-204
FSAVE/FNSAVE-Store FPU
State
9B DD /6
FSAVE
m94/108byte
Add clarification
phrase to existing
3-237
