INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
32
C15.
Built-in Self Test Always Gives Nonzero Result
Problem:
The Built-in Self Test (BIST) of the Celeron processor does not give a zero result to indicate a
passing test. Regardless of pass or fail status, bit 6 of the BIST result in the EAX register after running BIST is
set.
Implication:
Software which relies on a zero result to indicate a passing BIST will indicate BIST failure.
Workaround:
Mask bit 6 of the BIST result register when analyzing BIST results.
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
C16.
THERMTRIP# May Not Be Asserted as Specified
Problem:
THERMTRIP# is a signal on the Celeron processor which is asserted when the core reaches a
critical temperature during operation as detailed in the processor specification. The Celeron processor may
not assert THERMTRIP# until a much higher temperature than the one specified is reached.
Implication:
The THERMTRIP# feature is not functional on the Celeron processor. Note that this erratum
can only occur when the processor is running with a T
PLATE
temperature over the maximum specification of
75° C.
Workaround:
Avoid operation of the Celeron processor outside of the thermal specifications defined by the
processor specifications.
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
C17.
Cache State Corruption in the Presence of Page A/D-bit
Setting and Snoop Traffic
Problem:
If an operating system uses the Page Access and/or Dirty bit feature implemented in the Intel
architecture and there is a significant amount of snoop traffic on the bus, while the processor is setting the
Access and/or Dirty bit the processor may inappropriately change a single L1 cache line to the modified state.
Implication:
The occurrence of this erratum may result in cache incoherency, which may cause parity
errors, data corruption (with no parity error), unexpected application or operating system termination, or
system hangs.
Workaround:
It is possible for BIOS code to contain a workaround for this erratum.
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
