INTEL
®
CELERON® PROCESSOR SPECIFICATION UPDATE
45
C41.
UC Write May Be Reordered Around a Cacheable Write
Problem:
After a write occurs to a UC (uncacheable) region of memory, there exists a small window of
opportunity where a subsequent write transaction targeted for a UC memory region may be reordered in front
of a write targeted to a region of cacheable memory. This erratum can only occur during the following
sequence of bus transactions:
1.
A write to memory mapped as UC occurs
2.
A write to memory mapped as cacheable (WB or WT) which is present in Shared or Invalid state in the
L2 cache occurs
3.
During the bus snoop of the cacheable line, another store to UC memory occurs
Implication:
If this erratum occurs, the second UC write will be observed on the bus prior to the Bus
Invalidate Line (BIL) or Bus Read Invalidate Line (BRIL) transaction for the cacheable write. This presents a
small window of opportunity for a fast bus-mastering I/O device which triggers an action based on the second
UC write to arbitrate and gain ownership of the bus prior to the completion of the cacheable write, possibly
retrieving stale data.
Workaround:
It is possible for BIOS code to contain a workaround for this erratum.
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
C42.
Resume Flag May Not Be Cleared After Debug Exception
Problem:
The Resume Flag (RF) is normally cleared by the processor after executing an instruction which
causes a debug exception (#DB). In the process of determining whether the RF needs to be cleared after
executing the instruction, the processor uses an internal register containing stale data. The stale data may
unpredictably prevent the processor from clearing the RF.
Implication:
If this erratum occurs, further debug exceptions will be disabled.
Workaround:
None identified
Status:
For the steppings affected see the
Summary of Changes
at the beginning of this section.
