Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011 Datasheet Download Page 275

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Datasheet, Volume 2

275

Processor Configuration Registers

2.21.9

FECTL_REG—Fault Event Control Register

This register specifies the fault event interrupt message control bits.

B/D/F/Type:

0/0/0/VC0PREMAP

Address Offset:

38-3Bh

Reset Value:

80000000h

Access:

RW, RO-V

Size:

32 bits

BIOS Optimal Default

00000000h

Bit

Attr

Reset

Value

RST/

PWR

Description

Uncore

Interrupt Mask (IM)

0 = No masking of interrupt. When an interrupt condition is

detected, hardware issues an interrupt message (using the

Fault Event Data and Fault Event Address register values).

1 = This is the value on reset. Software may mask interrupt

message generation by setting this field. Hardware is

prohibited from sending the interrupt message when this field

is set.

RO-V

Uncore

Interrupt Pending (IP)

Hardware sets the IP field when it detects an interrupt condition,

which is defined as:

• When primary fault logging is active, an interrupt condition

occurs when hardware records a fault through one of the Fault

Recording registers and sets the PPF field in Fault Status

• When advanced fault logging is active, an interrupt condition

occurs when hardware records a fault in the first fault record

(at index 0) of the current fault log and sets the APF field in

the Fault Status register.

• Hardware detected error associated with the Invalidation

Queue, setting the IQE field in the Fault Status register.

• Hardware detected invalid Device-IOTLB invalidation

completion, setting the ICE field in the Fault Status register.

• Hardware detected Device-IOTLB invalidation completion time-

out, setting the ITE field in the Fault Status register.

If any of the status fields in the Fault Status register was already

set at the time of setting any of these fields, it is not treated as a

new interrupt condition.
The IP field is kept set by hardware while the interrupt message is

held pending. The interrupt message could be held pending due to

interrupt mask (IM field) being Set or other transient hardware

conditions.
The IP field is cleared by hardware as soon as the interrupt

message pending condition is serviced. This could be due to either:

• Hardware issuing the interrupt message due to either change

in the transient hardware condition that caused interrupt

message to be held pending, or due to

• Software clearing the IM field.

Software servicing all the pending interrupt status fields in the

Fault Status register as follows:

• When primary fault logging is active, software clearing the

Fault (F) field in all the Fault Recording registers with faults,

causing the PPF field in Fault Status register to be evaluated as

clear.

• Software clearing other status fields in the Fault Status

fields.

29:0

Reserved

Summary of Contents for 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011

Page 1: ...Document Number 324642 001 2nd Generation Intel Core Processor Family Desktop Datasheet Volume 2 Supporting Intel Core i7 i5 and i3 Desktop Processor Series This is Volume 2 of 2 January 2011...

Page 2: ...MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific s...

Page 3: ...mory Remapping 28 2 3 4 4 Hardware Remap Algorithm 28 2 3 4 5 Programming Model 28 2 3 5 PCI Express Configuration Address Space 32 2 3 6 PCI Express Graphics Attach PEG 33 2 3 7 Graphics Memory Addre...

Page 4: ...CAPID0_A Capabilities A Register 80 2 6 PCI Device 1 Function 0 2 Configuration Space 82 2 6 1 VID1 Vendor Identification Register 84 2 6 2 DID1 Device Identification Register 84 2 6 3 PCICMD1 PCI Com...

Page 5: ...ice 2 Configuration Space 128 2 8 1 VID2 Vendor Identification Register 129 2 8 2 DID2 Device Identification Register 129 2 8 3 PCICMD2 PCI Command Register 130 2 8 4 PCISTS2 PCI Status Register 131 2...

Page 6: ...7 2 10 33 PEG_CAPL PCI Express G Capability List Register 167 2 10 34 PEG_CAP PCI Express G Capabilities Register 168 2 10 35 DCAP Device Capabilities Register 168 2 10 36 DCTL Device Control Register...

Page 7: ...config Self Refresh Configuration Register 212 2 17 Memory Controller MMIO Registers Broadcast Group 213 2 17 1 PM_PDWN_Config Power down Configuration Register 213 2 17 2 PM_CMD_PWR Power Management...

Page 8: ...pability Register 264 2 21 4 GCMD_REG Global Command Register 266 2 21 5 GSTS_REG Global Status Register 269 2 21 6 RTADDR_REG Root Entry Table Address Register 270 2 21 7 CCMD_REG Context Command Reg...

Page 9: ...2 Extended Configuration Register Address Map 123 2 10 PCI Device 2 Configuration Register Address Map 128 2 11 Device 2 IO Register Address Map 140 2 12 PCI Device 6 Register Address Map 141 2 13 PC...

Page 10: ...10 Datasheet Volume 2 Revision History Revision Number Description Revision Date 001 Initial release January 2011...

Page 11: ...on the PCI Bus assigned for the processor socket This document describes these configuration space registers or device specific control and status registers CSRs only This document does NOT include M...

Page 12: ...Introduction 12 Datasheet Volume 2...

Page 13: ...le writing a 0 to a bit has no effect Hardware clears these bits RsvdP Reserved and Preserved These bits are reserved for future RW implementations and their value must not be modified by software Whe...

Page 14: ...arate configuration bit or other logic Note Mutually exclusive with Once modifier WO O RW Once After reset these bits can only be written by software once after which they become Read Only Note Mutual...

Page 15: ...iated Tilex Tiley linear reads writes to GMADR range are supported Write accesses to GMADR linear regions are supported from both DMI and PEG GMADR write accesses to tileX and tileY regions defined us...

Page 16: ...r using I O semantics the IGD and internal graphics instruction port registers can be acces sed Note this allows accessing the same registers as GTTMMADR The IOBAR can be used to issue writes to the G...

Page 17: ...SE GFX Stolen 0 256 MB ME UMA TOM GFX GTT Stolen BASE MESEG BASE 1 MB aligned 1 MB aligned OS invisible Reclaim 1 MB aligned for reclaim 1 MB aligned 4 GB FEC0_0000 1 MB aligned TOUUD BASE 1 MB aligne...

Page 18: ...stem BIOS Area 960 KB 1 MB Memory System BIOS Area 2 3 1 1 DOS Range 0h 9_FFFFh The DOS area is 640 KB 0000_0000h 0009_FFFFh in size and is always mapped to the main memory controlled by the MCH Figur...

Page 19: ...MI originated cycles to enable SMM space are not allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the VGA device DMI initiated write cycles are attempted as peer writ...

Page 20: ...nt to DRAM Graphics translated requests to this region are not allowed If such a mapping error occurs the request will be routed to C_0000h Writes will have the byte enables de asserted 2 3 2 Main Mem...

Page 21: ...s 2 3 2 3 Protected Memory Range PMR programmable For robust and secure launch of the MVMM the MVMM code and private data needs to be loaded to a memory region protected from bus master accesses Suppo...

Page 22: ...this protected range even if they passed the VTd translation The system will set up 0 to TSEG_BASE DPR size 1 for DMA traffic TSEG_BASE to TSEG_BASE DPR size as no DMA After some time software could...

Page 23: ...exceptions are 1 Addresses decoded to the egress port registers PXPEPBAR 2 Addresses decoded to the memory mapped range for internal MCH registers MCHBAR 3 Addresses decoded to the registers associat...

Page 24: ...ry Address Range DMI Interface subtractive decode FEF0_0000h 4 GB 2 MB MSI Interrupts FEE0_0000h PCI Express Configuration Space E000_0000h High BIOS FFE0_0000h FFFF_FFFFh 4 GB 4 GB 17 MB DMI Interfac...

Page 25: ...entry W orkstation Server SKUs of the processor and would be disabled in typical Desktop systems When disabled any access within entire APIC Configuration space FEC0_0000h to FECF_FFFFh is forwarded...

Page 26: ...of physical memory The ME stolen memory base is calculated by subtracting the amount of memory stolen by the Manageability Engine from TOM Top of Upper Usable DRAM TOUUD The Top of Upper Usable Dram...

Page 27: ...s range located just below the Manageability Engine s stolen memory 2 3 4 2 Indirect Accesses to MCHBAR Registers This access is similar to prior chipsets MCHBAR registers can be indirectly accessed u...

Page 28: ...35 20 THEN ADDRESS_OUT 38 20 ADDRESS_IN 38 20 REMAP_BASE 35 20 0000000b and TOLUD 31 20 ADDRESS_OUT 19 0 ADDRESS_IN 19 0 2 3 4 5 Programming Model The memory boundaries of interest are Bottom of Logi...

Page 29: ...GB minus 1 MB REMAPBASE 7F_FFFF_0000h default REMAPLIMIT 00_0000_0000h 0 GB boundary default Figure 2 5 Case 1 Less than 4 GB of Physical Memory no remap OS VISIBLE 4 GB GFX Stolen ME UMA Wasted Only...

Page 30: ...C000_000h 3 GB REMAPBASE 01_4000_0000h 5 GB REMAPLIMIT 01_7FF0_0000h 6 GB 1 Figure 2 6 Case 2 Greater than 4 GB of Physical Memory Main Memory Add Range OS VISIBLE 4 GB PCI Memory Add Range subtractiv...

Page 31: ...n size Addresses of MMIO region must not overlap with any part of the Logical Address Memory Remap range When TOM is equal to TOLUD remap is not needed and must be disabled by programming REMAPBASE to...

Page 32: ...other decodes have taken place Unmapped addresses between TOLUD and 4 GB Accesses that do not hit DRAM or PCI space are subtractive decoded to DMI Because the TOLUD register is used to mark the upper...

Page 33: ...Memory_Base_Address Address Memory_Limit_Address Prefetchable_Memory_Base_Address Address Prefetchable_Memory_Limit_Address The window size is programmed by the plug and play configuration software Th...

Page 34: ...an be accessed using this IOBAR The IOBAR is composed of an index register and a data register MMIO_Index MMIO_INDEX is a 32 bit register A 32 bit all bytes enabled I O write to this port loads the of...

Page 35: ...able SMM DRAM space the request will be remapped to address 000C_0000h with de asserted byte enables PCI Express and DMI Interface read accesses to the GMADR range are not supported therefore will hav...

Page 36: ...cycles should never occur If one does occur the transaction will complete with an UR completion status Similar to FSB processors I O reads that lie within 8 byte boundaries but cross 4 byte boundaries...

Page 37: ...ted cycles are not snooped The processor accepts accesses from DMI Interface to the following address ranges All snoop memory read and write accesses to Main DRAM including PAM region except stolen me...

Page 38: ...re routed in a peer fashion VCp Optionally enabled Supports priority snoop traffic only This VC is given higher priority atthe snoop VC arbiter Routed as an independentvirtual channel and treated inde...

Page 39: ...hrough VTd remap tables The remapbase remaplimit registers to not apply to VCm transactions Figure 2 7 Example DMI Upstream VC0 Memory Map A0000 BFFFF VGA GMADR FEE0_0000 FEEF_FFFF MSI TSEG_BASE mem w...

Page 40: ...es Sent to DRAM address 000C_0000h non snooped with byte enables all disabled Peer writes from PEG to DMI are not supported If PEG bus master enable is not set all reads and writes are treated as unsu...

Page 41: ...terface depends on the Legacy VGA configurations bits VGA Enable and MDAP For the remainder of this section PCI Express can refer to either the device 1 port functions or the device 6 port VGA range a...

Page 42: ...N bit 4 Internal Graphics VGA in Device 0 function 0 is enabled through register GGC bit 1 IGD I O accesses PCICMD2 04 05h IOAE bit 0 in Device 2 are enabled VGA I O decodes for IGD uses 16 address bi...

Page 43: ...dress and memory address ranges defined by the previously defined base and limit registers Forwarding of these accesses is also independent of the settings of the ISA Enable settings if this bit is 1...

Page 44: ...O locations listed above or their aliases will be forwarded to the DMI Interface even if the reference includes I O locations not listed above For I O reads which are split into multiple DWord access...

Page 45: ...ts These bits are labeled Reserved Software must deal correctly with fields that are reserved On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits bei...

Page 46: ...PCISTS PCI Status 0090h RO RW1C 8h RID Revision Identification 00h RO FW 9 Bh CC Class Code 060000h RO C Dh RSVD Reserved 0h RO Eh HDR Header Type 00h RO F 2Bh RSVD Reserved 0h RO 2C 2Dh SVID Subsyst...

Page 47: ...ress Register 00000000000 00000h RW KL RW L A0 A7h TOM Top of Memory 0000007FFFF 00000h RW KL RW L A8 AFh TOUUD Top of Upper Usable DRAM 00000000000 00000h RW KL RW L B0 B3h BDSM Base Data of Stolen M...

Page 48: ...Description 15 0 RO 8086h Uncore Vendor Identification Number VID PCI standard identification for Intel B D F Type 0 0 0 PCI Address Offset 2 3h Reset Value 0100h Access RO FW RO V Size 16 bits Bit At...

Page 49: ...ERR message is not generated by the Host for Device 0 This bit only controls SERR messaging for Device 0 Other integrated devices have their own SERRE bits to control error reporting for error conditi...

Page 50: ...I Address Offset 6 7h Reset Value 0090h Access RO RW1C Size 16 bits BIOS Optimal Default 00h Bit Attr Reset Value RST PWR Description 15 RW1C 0b Uncore Detected Parity Error DPE This bit is set when t...

Page 51: ...physically connect to PCI_A This bit is set to 1 indicating fast back to back capability so that the optimum setting for PCI_A is not limited by the Host 6 6 RO 0h Reserved 5 RO 0b Uncore 66 MHz Capab...

Page 52: ...ins the revision number of the processor The SRID is a 8 bit hardwired value assigned by Intel based on product stepping The SRID is not a directly addressable PCI register The SRID value is reflected...

Page 53: ...Bridge device This code has the value 06h indicating a Bridge device 15 8 RO 00h Uncore Sub Class Code SUBCC This is an 8 bit value that indicates the category of Bridge into which the Host Bridge dev...

Page 54: ...RW O Size 16 bits Bit Attr Reset Value RST PWR Description 15 0 RW O 0000h Uncore Subsystem Vendor ID SUBVID This field should be programmed during boot up to indicate the vendor of the system board...

Page 55: ...0000000h Bit Attr Reset Value RST PWR Description 63 39 RO 0h Reserved 38 12 RW 0000000h Uncore PCI Express Egress Port MMIO Base Address PXPEPBAR This field corresponds to bits 38 12 of the base addr...

Page 56: ...dress Offset 48 4Fh Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 0000000000h Bit Attr Reset Value RST PWR Description 63 39 RO 0h Reserved 38 15 RW 000000h Uncore Host Mem...

Page 57: ...engines are in iGFX Mode Device 2 Class Code is 030000h 13 10 RO 0h Reserved 9 8 RW L 0h Uncore GTT Graphics Memory Size GGMS This field is used to select the amount of Main Memory that is pre allocat...

Page 58: ...352 MB Ch 384 MB Dh 416 MB Eh 448MB Fh 480 MB 10h 512 MB Other Reserved 2 RO 0h Reserved 1 RW L 0b Uncore IGD VGA Disable IVD 0 Enable Device 2 IGD claims VGA memory and I O cycles the Sub Class Code...

Page 59: ...served 6 5 RO 0h Reserved 4 RW L 1b Uncore Internal Graphics Engine D2EN 0 Disabled Bus 0 Device 2 is disabled and hidden 1 Enabled Bus 0 Device 2 is enabled and visible This bit will be set to 0b and...

Page 60: ...reserved for MCHBAR is outside of PCIEXBAR space On reset this register is disabled and must be enabled by writing a 1 to theenable field in this register This base address shall be assigned on a boun...

Page 61: ...e configuration space and the PCI Express extended configuration space 27 RW V 0b Uncore 128MB Base Address Mask ADMSK128 This bit is either part of the PCI Express Base Address RW or part of the Addr...

Page 62: ...dress Offset 68 6Fh Reset Value 0000000000000000h Access RW Size 64 bits BIOS Optimal Default 000000000h Bit Attr Reset Value RST PWR Description 63 39 RO 0h Reserved 38 12 RW 0000000h Uncore DMI Base...

Page 63: ...rected to DMI WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses ar...

Page 64: ...E attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 81...

Page 65: ...WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 8...

Page 66: ...E attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 83...

Page 67: ...E attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 84...

Page 68: ...WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 8...

Page 69: ...WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 8...

Page 70: ...backbone If the VGA enable bit is set and MDA is not present then accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through Device 6 Function 0 if the address is within the corres...

Page 71: ...I O 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases will remain on the backbo...

Page 72: ...I O 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases will remain on the backbo...

Page 73: ...I O 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases will remain on the backbo...

Page 74: ...window is disabled These bits are Intel TXT lockable 19 1 RO 0h Reserved 0 RW KL 0b Uncore Lock LOCK This bit will lock all writeable settings in this register including itself B D F Type 0 0 0 PCI Ad...

Page 75: ...ST PWR Description 63 39 RO 0h Reserved 38 20 RW L 7FFFFh Uncore Top of Memory TOM This register reflects the total amount of populated physical memory This is NOT necessarily the highest main memory...

Page 76: ...Value 0000000000000000h Access RW KL RW L Size 64 bits BIOS Optimal Default 00000000000h Bit Attr Reset Value RST PWR Description 63 39 RO 0h Reserved 38 20 RW L 00000h Uncore TOUUD TOUUD This registe...

Page 77: ...RW L 000h Uncore Graphics Base of Stolen Memory BDSM This register contains bits 31 20 of the base address of stolen DRAM memory BIOS determines the base of graphics stolen memory by subtracting the...

Page 78: ...tolen Memory Size set to 2 MB BIOS knows the OS requires 1G of PCI space BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable by the system This 20 MB range at the very top of add...

Page 79: ...ory plus one byte or the minimum address allocated for PCI memory Address bits 19 0 are assumed to be 0_0000h for the purposes of address comparison The Host interface positively decodes an address to...

Page 80: ...eserved 24 RO FW 0b Reserved 23 RO KFW 0b Uncore VTd Disable VTDD 0 Enable VTd 1 Disable VTd 22 RO FW 0b Reserved 21 RO FW 0b Reserved 20 19 RO FW 00b Reserved 18 RO FW 0b Reserved 17 RO FW 0b Reserve...

Page 81: ...ield 6 4 of the Clocking Configuration registers MCHBAR Offset C00h Any attempt to write an unsupported value will be ignored 000 MC capable of All memory frequencies 101 MC capable of up to DDR3 1600...

Page 82: ...h RSVD Reserved 0h RO 1Ch IOBASE1 I O Base Address F0h RW 1Dh IOLIMIT1 I O Limit Address 00h RW 1E 1Fh SSTS1 Secondary Status 0000h RW1C RO 20 21h MBASE1 Memory Base Address FFF0h RW 22 23h MLIMIT1 Me...

Page 83: ...AC AFh RSVD Reserved 0h RO B0 B1h LCTL Link Control 0000h RW RO RW V B2 B3h LSTS Link Status 1001h RO V RW1C RO B4 B7h SLOTCAP Slot Capabilities 00040000h RW O RO B8 B9h SLOTCTL Slot Control 0000h RO...

Page 84: ...evice B D F Type 0 1 0 2 PCI Address Offset 0 1h Reset Value 8086h Access RO Size 16 bits Bit Attr Reset Value RST PWR Description 15 0 RO 8086h Uncore Vendor Identification VID PCI standard identific...

Page 85: ...her through this bit or through the PCI Express specific bits in the Device Control Register In addition for Type 1 configuration space header devices this bit when set enables transmission by the pri...

Page 86: ...nsupported Request status or Master abort in its completion packet 1 This device is allowed to issue requests to its primary bus Completions for previously issued memory read requests on the primary b...

Page 87: ...affect this field 13 RO 0b Uncore Received Master Abort Status RMAS This bit is Set when a Requester receives a Completion with Unsupported Request Completion Status On a Function with a Type 1 Config...

Page 88: ...7 RO 0b Uncore Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 6 6 RO 0h Reserved 5 RO 0b Uncore 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 4 RO 1b Un...

Page 89: ...cation Update for the value of the RID register 3 0 RO FW 0h Uncore Revision Identification Number RID This is an 8 bit value that indicates the revision identification number for the root port Refer...

Page 90: ...ut has no impact on any PCI Express device functionality B D F Type 0 1 0 2 PCI Address Offset Eh Reset Value 81h Access RO Size 8 bits Bit Attr Reset Value RST PWR Description 7 0 RO 81h Uncore Heade...

Page 91: ...ing of configuration cycles to PCI Express G B D F Type 0 1 0 2 PCI Address Offset 19h Reset Value 00h Access RW Size 8 bits Bit Attr Reset Value RST PWR Description 7 0 RW 00h Uncore Secondary Bus Nu...

Page 92: ...ss decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range will be at the top of a 4 KB aligned address block B D F Type 0 1 0 2 PCI Address Offset 1Ch Reset Va...

Page 93: ...nitiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status 12 RW1C 0b Uncore Received Target Abort RTA This bit is set when the Secondary Side for Typ...

Page 94: ...s register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the...

Page 95: ...uctures of the graphics controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space attr...

Page 96: ...A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined m...

Page 97: ...de address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note Prefetchable memory range is supported to allow...

Page 98: ...following formula PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 39 bit address The lower 7...

Page 99: ...2 PCI Address Offset 34h Reset Value 88h Access RO Size 8 bits Bit Attr Reset Value RST PWR Description 7 0 RO 88h Uncore First Capability CAPPTR1 The first capability in the list is the Subsystem ID...

Page 100: ...ts interrupt pin The Interrupt Pin register tells which interrupt pin the device or device function uses 1h Corresponds to INTA Default 2h Corresponds to INTB 3h Corresponds to INTC 4h Corresponds to...

Page 101: ...s the response by the root port to an I O access issued by the processor that target ISA I O addresses This applies only to I O addresses that are enabled by the IOBASE and IOLIMIT registers 0 All add...

Page 102: ...Current AUXC Hardwired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements 21 RO 0b Uncore Device Specific Initialization DSI Hardwired to 0 to indicate that special initializat...

Page 103: ...t this device does not generate PME assertion from any D state 0 PME generation not possible from any D State 1 PME generation enabled from any D State The setting of this bit has no effect on hardwar...

Page 104: ...vice also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the D0 state in order to be fully functional When the Power State is other than D0 the bridge wi...

Page 105: ...om the PCI PM capability to the PCI Express capability B D F Type 0 1 0 2 PCI Address Offset 8C 8Fh Reset Value 00008086h Access RW O Size 32 bits Bit Attr Reset Value RST PWR Description 31 16 RW O 0...

Page 106: ...nerating a 64 bit memory address This may need to change in future implementations when addressable system memory exceeds the 32b 4GB limit 6 4 RW 000b Uncore Multiple Message Enable MME System softwa...

Page 107: ...ccess RW Size 16 bits Bit Attr Reset Value RST PWR Description 15 0 RW 0000h Uncore Message Data MD Base message data pattern assigned by system software and used to handle an MSI from the device When...

Page 108: ...a slot connection is not implemented 7 4 RO 4h Uncore Device Port Type DPT Hardwired to 4h to indicate root port of PCI Express Root Complex 3 0 RO 2h Uncore PCI Express Capability Version PCIECV Hard...

Page 109: ...e Relaxed Ordering ROE 3 RW 0b Uncore Unsupported Request Reporting Enable URRE When set allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an unmasked Uns...

Page 110: ...the Fatal Error Detected bit is set according to the setting of the Unsupported Request Error Severity bit In production systems setting the Fatal Error Detected bit is not an option as support for AE...

Page 111: ...en Set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width Devices that do not implement the ability a...

Page 112: ...urns 0 when read This bit is cleared automatically no need to write a 0 4 RW 0b Uncore Link Disable LD 0 Normal operation 1 Link is disabled Forces the TXTSSM to transition to the Disabled state using...

Page 113: ...when the Link is in the process of retraining for some other reason Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an TXTSSM time...

Page 114: ...W1C RO Size 16 bits BIOS Optimal Default 0h Bit Attr Reset Value RST PWR Description B D F Type 0 1 0 2 PCI Address Offset B4 B7h Reset Value 00040000h Access RW O RO Size 32 bits Bit Attr Reset Value...

Page 115: ...on This is a form factor specific capability This bit is an indication to the operating system to allow for such removal without impacting continued software operation 4 RO 0b Uncore Reserved for Powe...

Page 116: ...t per the defined encodings Reads of this field must reflect the value from the latest write even if the corresponding hotplug command is not complete unless software issues a write without waiting fo...

Page 117: ...eted notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register when set to 1b this bit enables software notification when a hot plug command is complet...

Page 118: ...ence detect mechanism and if present any out of band presence detect mechanism defined for the slot s corresponding form factor Note that the in band presence detect mechanism requires that power be a...

Page 119: ...ower fault detection is implemented this bit is set when the Power Controller detects a power fault at this slot Note that depending on hardware capability it is possible that a power fault can be det...

Page 120: ...SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself 1 0 RO 0h Reserved B D F Type 0 1 0 2 PCI Address...

Page 121: ...must be monotonic with a non zero slope The value of n must be greater than 3 and less than 7 At least two of these must be below the normal operating range n 200 400 mV for full swing and 100 200 mV...

Page 122: ...d included in the Supported Link Speeds field the result is undefined The Reset Value of this field is the highest link speed supported by the component as reported in the Supported Link Speeds field...

Page 123: ...C0RCAP VC0 Resource Capability 00000001h RO 114 117h VC0RCTL VC0 Resource Control 800000FFh RO RW 118 119h RSVD Reserved 0h RO 11A 11Bh VC0RSTS VC0 Resource Status 0002h RO V 11C 207h RSVD Reserved 20...

Page 124: ...cture A value of 0 indicates that the table is not present due to fixed VC priority 23 8 RO 0h Reserved 7 0 RO 00h Uncore Reserved for VC Arbitration Capability VCAC B D F Type 0 1 0 2 MMR Address Off...

Page 125: ...rt Arbitration Supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that...

Page 126: ...press Endpoint devices or Root Ports that do not support peer to peer traffic The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capabili...

Page 127: ...ation It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 st...

Page 128: ...CLS Cache Line Size 00h RO Dh MTXT2 Master Latency Timer 00h RO Eh HDR2 Header Type 00h RO Fh RSVD Reserved 0h RO 10 17h GTTMMADR Graphics Translation Table Memory Mapped Range Address 000000000 00000...

Page 129: ...ion Number VID PCI standard identification for Intel B D F Type 0 2 0 PCI Address Offset 2 3h Reset Value 0102h Access RO V RO FW Size 16 bits Bit Attr Reset Value RST PWR Description 15 4 RO FW 010h...

Page 130: ...re Address Data Stepping Enable ADSTEP Not Implemented Hardwired to 0 6 RO 0b Uncore Parity Error Enable PERRE Not Implemented Hardwired to 0 Since the IGD belongs to the category of devices that does...

Page 131: ...Uncore Signaled Target Abort Status STAS Hardwired to 0 The IGD does not use target abort semantics 10 9 RO 00b Uncore DEVSEL Timing DEVT Not applicable These bits are hardwired to 00 8 RO 0b Uncore...

Page 132: ...gister 3 0 RO FW 0h Uncore Revision Identification Number RID Four LSB of RID Refer to the 2nd Generation Intel Core Processor Family Desktop Specification Update for the value of the RID register B D...

Page 133: ...r does not use the Memory Write and Invalidate command and in general does not perform operations based on cache line size B D F Type 0 2 0 PCI Address Offset Dh Reset Value 00h Access RO Size 8 bits...

Page 134: ...egion in order to invalidate any cached translations within the various TLBs implemented on chip The allocation is for 4 MB and the base address is defined by bits 38 22 B D F Type 0 2 0 PCI Address O...

Page 135: ...o address signals 38 29 28 RW L 0b FLR Uncore 512 MB Address Mask ADMSK512 This Bit is either part of the Memory Base Address RW or part of the Address Mask RO depending on the value of MSAC 2 1 See M...

Page 136: ...8 13 SVID2 Subsystem Vendor Identification Register This register is used to uniquely identify the subsystem where the PCI device resides B D F Type 0 2 0 PCI Address Offset 20 23h Reset Value 000000...

Page 137: ...ication SUBID This value is used to identify a particular subsystem This field should be programmed by BIOS during boot up Once written this register becomes Read Only This register can only be cleare...

Page 138: ...tings of Latency Timers B D F Type 0 2 0 PCI Address Offset 3Eh Reset Value 00h Access RO Size 8 bits Bit Attr Reset Value RST PWR Description 7 0 RO 00h Uncore Minimum Grant Value MGV The IGD does no...

Page 139: ...Size 8 bits BIOS Optimal Default 0h Bit Attr Reset Value RST PWR Description 7 3 RO 0h Reserved 2 RW K 0b Uncore Untrusted Aperture Size High LHSASH This field is used in conjunction with LHSASL The d...

Page 140: ...EX register Table 2 11 Device 2 IO Register Address Map Address Offset Register Symbol Register Name Reset Value Access 0 3h Index MMIO Address Register 00000000h RW 4 7h Data MMIO Data Register 00000...

Page 141: ...I O Base Address F0h RW 1Dh IOLIMIT6 I O Limit Address 00h RW 1E 1Fh SSTS6 Secondary Status 0000h RW1C RO 20 21h MBASE6 Memory Base Address FFF0h RW 22 23h MLIMIT6 Memory Limit Address 0000h RW 24 25...

Page 142: ...ilities 00008000h RO RW O A8 A9h DCTL Device Control 0000h RO RW AA ABh DSTS Device Status 0000h RO RW1C AC AFh RSVD Reserved 0h RO B0 B1h LCTL Link Control 0000h RO RW RW V B2 B3h LSTS Link Status 10...

Page 143: ...fies any PCI device B D F Type 0 6 0 PCI Address Offset 0 1h Reset Value 8086h Access RO Size 16 bits Bit Attr Reset Value RST PWR Description 15 0 RO 8086h Uncore Vendor Identification VID PCI standa...

Page 144: ...either through this bit or through the PCI Express specific bits in the Device Control register In addition for Type 1 configuration space header devices this bit when set enables transmission by the...

Page 145: ...return Unsupported Request status or Master abort in its completion packet 1 This device is allowed to issue requests to its primary bus Completions for previously issued memory read requests on the p...

Page 146: ...his field 13 RO 0b Uncore Received Master Abort Status RMAS This bit is set when a Requester receives a Completion with Unsupported Request Completion Status On a Function with a Type 1 Configuration...

Page 147: ...rt 7 RO 0b Uncore Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 6 6 RO 0h Reserved 5 RO 0b Uncore 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 4 RO 1b...

Page 148: ...ly Desktop Specification Update for the value of the RID register 3 0 RO FW 0h Uncore Revision Identification Number RID This is an 8 bit value that indicates the revision identification number for th...

Page 149: ...s but has no impact on any PCI Express device functionality B D F Type 0 6 0 PCI Address Offset Eh Reset Value 01h Access RO Size 8 bits Bit Attr Reset Value RST PWR Description 7 0 RO 01h Uncore Head...

Page 150: ...apping of configuration cycles to PCI Express G B D F Type 0 6 0 PCI Address Offset 19h Reset Value 00h Access RW Size 8 bits Bit Attr Reset Value RST PWR Description 7 0 RW 00h Uncore Secondary Bus N...

Page 151: ...address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range will be at the top of a 4 KB aligned address block B D F Type 0 6 0 PCI Address Offset 1Ch Rese...

Page 152: ...nitiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status 12 RW1C 0b Uncore Received Target Abort RTA This bit is set when the Secondary Side for Typ...

Page 153: ...his register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus th...

Page 154: ...ructures of the graphics controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space att...

Page 155: ...s A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined...

Page 156: ...e address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is supported to al...

Page 157: ...ond to address bits A 31 20 of the 39 bit address The lower 7 bits of the Upper Base Address register are read write and correspond to address bits A 38 32 of the 39 bit address This register must be...

Page 158: ...memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges th...

Page 159: ...his register as it initializes and configures the system The value indicates to which input of the system interrupt controller this device s interrupt pin is connected B D F Type 0 6 0 PCI Address Off...

Page 160: ...Uncore Primary Discard Timer PDT Not Applicable or Implemented Hardwired to 0 7 RO 0b Uncore Fast Back to Back Enable FB2BEN Not Applicable or Implemented Hardwired to 0 6 RW 0b Uncore Secondary Bus...

Page 161: ...e defined by the IOBASE and IOLIMIT registers 1 RW 0b Uncore SERR Enable SERREN 0 No forwarding of error messages from secondary side to primary side that could result in an SERR 1 ERR_COR ERR_NONFATA...

Page 162: ...Auxiliary Current AUXC Hardwired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements 21 RO 0b Uncore Device Specific Initialization DSI Hardwired to 0 to indicate that special in...

Page 163: ...evice does not generate PME assertion from any D state 0 Disable PME generation not possible from any D State 1 Enable PME generation enabled from any D State The setting of this bit has no effect on...

Page 164: ...device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the D0 state in order to be fully functional When the Power State is other than D0 the bridge...

Page 165: ...m the PCI PM capability to the PCI Express capability B D F Type 0 6 0 PCI Address Offset 8C 8Fh Reset Value 00008086h Access RW O Size 32 bits Bit Attr Reset Value RST PWR Description 31 16 RW O 0000...

Page 166: ...nerating a 64 bit memory address This may need to change in future implementations when addressable system memory exceeds the 32b 4 GB limit 6 4 RW 000b Uncore Multiple Message Enable MME System softw...

Page 167: ...e 0000h Access RW Size 16 bits Bit Attr Reset Value RST PWR Description 15 0 RW 0000h Uncore Message Data MD Base message data pattern assigned by system software and used to handle an MSI from the de...

Page 168: ...a slot connection is not implemented 7 4 RO 4h Uncore Device Port Type DPT Hardwired to 4h to indicate root port of PCI Express Root Complex 3 0 RO 2h Uncore PCI Express Capability Version PCIECV Har...

Page 169: ...ROE 3 RW 0b Uncore Unsupported Request Reporting Enable URRE When set this bit allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an unmasked Unsupported R...

Page 170: ...bit or the Fatal Error Detected bit is set according to the setting of the Unsupported Request Error Severity bit In production systems setting the Fatal Error Detected bit is not an option as support...

Page 171: ...h Disable HAWD When Set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width Devices that do not implem...

Page 172: ...turns 0 when read This bit is cleared automatically no need to write a 0 4 RW 0b Uncore Link Disable LD 0 Normal operation 1 Link is disabled Forces the TXTSSM to transition to the Disabled state usin...

Page 173: ...hen the Link is in the process of retraining for some other reason Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an TXTSSM time o...

Page 174: ...O V RO Size 16 bits BIOS Optimal Default 0h Bit Attr Reset Value RST PWR Description B D F Type 0 6 0 PCI Address Offset B4 B7h Reset Value 00040000h Access RW O RO Size 32 bits Bit Attr Reset Value R...

Page 175: ...ication This is a form factor specific capability This bit is an indication to the operating system to allow for such removal without impacting continued software operation 4 RO 0b Uncore Reserved for...

Page 176: ...ined encodings Reads of this field must reflect the value from the latest write even if the corresponding hotplug command is not complete unless software issues a write without waiting for the previou...

Page 177: ...Reserved for Command Completed Interrupt Enable CCI If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register when set to 1b this...

Page 178: ...presence detect mechanism and if present any out of band presence detect mechanism defined for the slot s corresponding form factor Note that the in band presence detect mechanism requires that power...

Page 179: ...ted this bit is set when the Power Controller detects a power fault at this slot Note that depending on hardware capability it is possible that a power fault can be detected at any time independent of...

Page 180: ...h RSVD Reserved 0h RO 110 113h VC0RCAP VC0 Resource Capability 00000001h RO 114 117h VC0RCTL VC0 Resource Control 800000FFh RO RW 118 119h RSVD Reserved 0h RO 11A 11Bh VC0RSTS VC0 Resource Status 0002...

Page 181: ...ty Structure A value of 0 indicates that the table is not present due to fixed VC priority 23 8 RO 0h Reserved 7 0 RO 00h Uncore Reserved for VC Arbitration Capability VCAC B D F Type 0 6 0 MMR Addres...

Page 182: ...itration supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that do not...

Page 183: ...press Endpoint devices or Root Ports that do not support peer to peer traffic The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capabili...

Page 184: ...VC0NP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization...

Page 185: ...25h RSVD Reserved 0h RO 26 27h DMIVC1RSTS DMI VC1 Resource Status 0002h RO V 28 2Bh DMIVCPRCAP DMI VCp Resource Capability 00000001h RO 2C 2Fh DMIVCPRCTL DMI VCp Resource Control 02000000h RO RW 30 3...

Page 186: ...Reset Value Access B D F Type 0 0 0 DMIBAR Address Offset 0 3h Reset Value 04010002h Access RO Size 32 bits Bit Attr Reset Value RST PWR Description 31 20 RO 040h Uncore Pointer to Next Capability PNC...

Page 187: ...Count LPEVCC This field indicates the number of extended Virtual Channels in addition to the default VC belonging to the low priority VC LPVC group that has the lowest priority with respect to other V...

Page 188: ...me such as Round Robin Others Reserved See the PCI express specification for more details 0 RO 0b Uncore Reserved for Load VC Arbitration Table LVCAT B D F Type 0 0 0 DMIBAR Address Offset 10 13h Rese...

Page 189: ...service Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource Because only bit 0 of that field is asserted This...

Page 190: ...ully exits the FC_INIT2 state BIOS Requirement Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a...

Page 191: ...Channel in both Components on a Link before re enabling the Virtual Channel 30 27 RO 0h Reserved 26 24 RW 001b Uncore Virtual Channel 1 ID VC1ID Assigns a VC ID to the VC resource Assigned value must...

Page 192: ...rtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negoti...

Page 193: ...k 2 To disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link 3 Software must ensure that no traffic is using a Virtual Channel at the time...

Page 194: ...VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling Software may use this bit when enabling or disabling the VC This bit indicates the statu...

Page 195: ...ss port of the component to provide arbitration to this Root Complex Element 23 16 RW O 00h Uncore Component ID CID This field identifies the physical component that contains this Root Complex Element...

Page 196: ...Value will likely be correct because the DMI RCRB in the PCH will likely be associated with the default egress port for the PCH meaning it will be assigned port number 0 23 16 RW O 00h Uncore Target...

Page 197: ...ns this element as specified by the target component ID 23 16 RW O 00h Uncore Target Component ID TCID This field identifies the physical or logical component that is targeted by this link entry BIOS...

Page 198: ...More than 64 s Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate and undesired value from ever existing 14 12 RW O 010...

Page 199: ...Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the L0s state and when in the Recovery state This mode provides external devices such as logic analyzers monito...

Page 200: ...o the Retrain Link bit but Link training has not yet begun Hardware clears this bit when the TXTSSM exits the Configuration Recovery state once Link training is complete 10 10 RO 0h Reserved 9 4 RO V...

Page 201: ...ulti Function device associated with an Upstream Port the bit in Function 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is...

Page 202: ...it to 1 in both components on a link and then initiating a hot reset on the link 3 0 RWS 2h Powerg ood Target Link Speed TLS For Downstream ports this field sets an upper limit on link operational spe...

Page 203: ...Reset Value 0000h Access RO V Size 16 bits BIOS Optimal Default 0000h Bit Attr Reset Value RST PWR Description 15 1 RO 0h Reserved 0 RO V 0b Uncore Current De emphasis Level CURDELVL When the Link is...

Page 204: ...dress Offset Register Symbol Register Name Reset Value Access 0 40AFh RSVD Reserved 40B0 40B3h PM_PDWN_config_C0 Power down Configuration 00000000h RW L 40B4 40C7h RSVD Reserved 40D0 438Fh RSVD Reserv...

Page 205: ...in order to use the maximum no refresh period possible 11 8 RW L 8h Uncore Refresh high priority WM Refresh_HP_WM tREFI count level that turns the refresh priority to high default is 8 7 0 RW L 0Fh Un...

Page 206: ...4698 469Bh TC_RFTP_C1 Refresh Parameters 46B41004h RW L 469C 438Fh RSVD Reserved B D F Type 0 0 0 MCHBAR MC1 Address Offset 44B0 44B3h Default Value 00000000h Access RW L Size 32 bits BIOS Optimal De...

Page 207: ...order to use the maximum no refresh period possible 11 8 RW L 8h Uncore Refresh high priority WM Refresh_HP_WM tREFI count level that turns the refresh priority to high default is 8 7 0 RW L 0Fh Unco...

Page 208: ...of credits for GSA VC1 completions 26 24 RW L 1h Uncore GSA VC0 Minimum Completion Credits GSAVC0 Minimum number of credits for GSA VC0 completions 23 21 RW L 1h Uncore PEG60 VC0 Minimum Completion C...

Page 209: ...l Register Name Reset Value Access 0 4FFFh RSVD Reserved 0h RO 5000 5003h MAD_CHNL Address decoder Channel Configuration 00000024h RW L 5004 5007h MAD_DIMM_ch0 Address Decode Channel 0 00600000h RW L...

Page 210: ...mode Enh_Interleave 0 Off 1 On 21 RW L 1b Uncore Rank Interleave RI 0 Off 1 On 20 RW L 0b Uncore DIMM B DDR Width DBW DIMM B width of DDR chips 0 X8 chips 1 X16 chips 19 RW L 0b Uncore DIMM A DDR Wid...

Page 211: ...leave mode Enh_Interleave 0 Off 1 On 21 RW L 1b Uncore Rank Interleave RI 0 Off 1 On 20 RW L 0b Uncore DIMM B DDR width DBW DIMM B width of DDR chips 0 X8 chips 1 X16 chips 19 RW L 0b Uncore DIMM A DD...

Page 212: ...ult 0000h Bit Attr Reset Value RST PWR Description 31 17 RO 0h Reserved 16 RW L 1 Uncore Self refresh Enable This control bit is an INTEL RESERVED bit It is for test and debug purposes only This bit e...

Page 213: ...Bh PM_BW_LIMIT_config BW Limit Configuration FFFF03FFh RW L 4F8C 4F8Fh RSVD Reserved FF1D1519h RW L B D F Type 0 0 0 MCHBAR_MCBCAST Address Offset 4CB0 4CB3h Default Value 00000000h Access RW L Size 3...

Page 214: ...ite command PWR_CAS_W 15 8 RW LV 00h Uncore Power contribution of CAS Read command PWR_CAS_R 7 0 RW LV 00h Uncore Power contribution of RAS command and PRE command PWR_RAS_PRE Power contribution of RA...

Page 215: ...nt Control Register 80000000h RW RO V 3C 3Fh FEDATA_REG Fault Event Data Register 00000000h RW 40 43h FEADDR_REG Fault Event Address Register 00000000h RW 44 47h FEUADDR_REG Fault Event Upper Address...

Page 216: ...REG IOTLB Invalidate Register 0200000000 000000h RW V RW RO V 110 1FFh RSVD Reserved 0h RO 200 207h FRCDL_REG Fault Recording Low Register 0000000000 000000h ROS V 208 20Fh FRCDH_REG Fault Recording H...

Page 217: ...emapping hardware unit in the platform The maximum number of fault recording registers per remapping hardware unit is 256 39 RO 0b Uncore Page Selective Invalidation PSI 0 Hardware supports only domai...

Page 218: ...ns requests to address above 2 x 1 1 from allowed devices return a null Translation Completion Data Entry with R W 0 Guest addressability for a given DMA request is limited to the minimum of the value...

Page 219: ...Uncore Required Write Buffer Flushing RWBF 0 No write buffer flushing is needed to ensure changes to memory resident structures are visible to hardware 1 Software must explicitly flush the write buff...

Page 220: ...st IOTLB invalidation register is calculated as X 16 Y 7 RO 0b Uncore Snoop Control SC 0 Hardware does not support 1 setting of the SNP field in the page table entries 1 Hardware supports the 1 settin...

Page 221: ...upports queued invalidations 0 RO 0b Uncore Coherency C This field indicates if hardware access to the root context page table and interrupt remap structures are coherent snooped or not 0 Hardware acc...

Page 222: ...and reflecting the status of the command through the TES field in the Global Status register The value returned on a read of this field is undefined 30 WO 0b Uncore Set Root Table Pointer SRTP Softwar...

Page 223: ...nter must be set in hardware through the SFL field before enabling advanced fault logging Hardware reports the status of the advanced fault logging enable operation through the AFLS field in the Globa...

Page 224: ...g or re enabling after disabling interrupt remapping hardware through the IRE field After a Set Interrupt Remap Table Pointer operation software must globally invalidate the interrupt entry cache This...

Page 225: ...lobal Command register 1 Set by hardware when hardware completes the Set Fault Log Pointer operation using the value provided in the Advanced Fault Log register 28 RO 0b Uncore Advanced Fault Logging...

Page 226: ...nabled and Extended Interrupt Mode x2APIC mode is not enabled 0 Compatibility format interrupts are blocked 1 Compatibility format interrupts are processed as pass through bypassing interrupt remappin...

Page 227: ...invalidation requests pending at this remapping hardware unit Since information from the context cache may be used by hardware to tag IOTLB entries software must perform domain selective or global inv...

Page 228: ...lidations The following encodings are defined for this field 00 No bits in the SID field masked 01 Mask most significant bit of function number in the SID field 10 Mask two most significant bit of fun...

Page 229: ...ardware received an unexpected or invalid Device IOTLB invalidation completion This could be due to either an invalid ITag or invalid source id in an invalidation completion response At this time a fa...

Page 230: ...lds across all the fault recording registers of this remapping hardware unit 0 No pending faults in any of the fault recording registers 1 One or more fault recording registers has pending faults The...

Page 231: ...ter Hardware detected error associated with the Invalidation Queue setting the IQE bit in the Fault Status register Hardware detected invalid Device IOTLB invalidation completion setting the ICE bit i...

Page 232: ...orting only 16 bit interrupt data may treat this field as RsvdZ 15 0 RW 0000h Uncore Interrupt Message Data IMD Data value in the interrupt request B D F Type 0 0 0 GFXVTBAR Address Offset 40 43h Rese...

Page 233: ...Address FLA This field specifies the base of 4 KB aligned fault log region in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Software specifies t...

Page 234: ...enabled all DMA requests accessing protected memory regions are blocked When DMA remapping is enabled DMA requests processed as pass through Translation Type value of 10b in Context Entry and accessin...

Page 235: ...ds on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding the most significant zero bit position with 0 in the value read back from...

Page 236: ...the value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The Protected low memory base and limit registers functions as follows Programming the protected l...

Page 237: ...iting all 1 s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of this register are decoded by hardware as...

Page 238: ...e limit register is decoded by hardware as all 1s The protected high memory base limit registers functions as follows Programming the protected low memory base and limit registers with the same value...

Page 239: ...ccess RO V Size 64 bits BIOS Optimal Default 0000000000000h Bit Attr Reset Value RST PWR Description 63 19 RO 0h Reserved 18 4 RO V 0000h Uncore Queue Head QH This field specifies the offset 128 bit a...

Page 240: ...39 RO 0h Reserved 38 12 RW L 0000000h Uncore Invalidation Queue Base Address IQA This field points to the base of 4 KB aligned invalidation request queue Hardware ignores and does not implement bits 6...

Page 241: ...hen this field is set 30 RO V 0b Uncore Interrupt Pending IP Hardware sets the IP bit when it detects an interrupt condition Interrupt condition is defined as An Invalidation Wait Descriptor with Inte...

Page 242: ...RST PWR Description 31 16 RW L 0000h Uncore Extended Interrupt Message Data EIMD This field is valid only for implementations supporting 32 bit interrupt data fields Hardware implementations supportin...

Page 243: ...res and does not implement bits 63 HAW where HAW is the host address width Reads of this field returns value that was last programmed to it 11 RW L 0b Uncore Extended Interrupt Mode Enable EIME This f...

Page 244: ...hardware 0 Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware must fl...

Page 245: ...on requests when there is a context cache invalidation request pending at this remapping hardware unit Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability registe...

Page 246: ...he DRD field is reported as clear in the Capability register When the DRD field is reported as set in the Capability register the following encodings are supported for this bit 0 Hardware may complete...

Page 247: ...Value 0000000000000000h Access ROS V Size 64 bits BIOS Optimal Default 0000000000000000h Bit Attr Reset Value RST PWR Description 63 12 ROS V 00000000 00000h Powerg ood Fault Info FI When the Fault Re...

Page 248: ...r fields When this bit is set hardware may collapse additional faults from the same source id SID Software writes the value read from this field to clear it 62 ROS V 0b Powerg ood Type T Type of the f...

Page 249: ...0000000h Access RO RO KFW RW KL RW L Size 32 bits BIOS Optimal Default 0000h Bit Attr Reset Value RST PWR Description 31 RW KL 0b Uncore DMA Remap Engine Policy Lock Down DMAR_LCKDN This bit protects...

Page 250: ...erved 00000000h RW 5888 588B MEM_TRML_THRE SHOLDS_CONFIG Memory Thermal Thresholds Configuration 00E4D5D0h RW 588C 589Fh RSVD Reserved 58A0 58A3 MEM_TRML_STAT US_REPORT Memory Thermal Status Report 00...

Page 251: ...ion of the memory BW to temperature The units are given in 1 power 2 44 21 12 RW 0C8h Uncore VTS time constant VTS_TIME_CONSTANT This factor is relevant only for BW based temperature estimation It is...

Page 252: ...ritical Temperature TEMP CRITICAL_TH This register is read by PCODE only during Reset Phase 4 NOTE The threshold values must be programmed such that WARM_TH HOT_TH CRITICAL_TH B D F Type 0 0 0 MCHBAR...

Page 253: ...core Double Self refresh DSR 0 Normal self refresh 1 Double self refresh 23 16 RO V 00h Reserved 15 8 RO V 00h Uncore Channel 1 Status CHANNEL1_STATUS The format is for each channel is defined as foll...

Page 254: ...ure CHANNEL1_ESTIMATED_MAX_TEMPERATURE VTS Estimated Temperature in Degrees C 7 0 RO V 00h Uncore Channel 0 VTS Estimated Max Temperature CHANNEL0_ESTIMATED_MAX_TEMPERATURE VTS Estimated Temperature i...

Page 255: ...the current RP state 7 0 RO V 00h Uncore RP State VID RP_STATE_VID VID of the current RP state B D F Type 0 0 0 MCHBAR PCU Address Offset 5998 599Bh Default Value 00000000h Access RO FW Size 32 bits B...

Page 256: ...for future use 29 24 RWS 00h Powerg ood MPLL Shutdown Latency Time WM3 Number of microseconds to access memory if memory is in Self Refresh SR with MDLLs and Memory PLLs shut off 0 5us granularity 00h...

Page 257: ...hen Memory is in Self Refresh The Display LP1 latency and watermark values GTTMMADR offset 45118h should be programmed to match the latency in this register 7 6 RWS 00b Powerg ood Reserved for Future...

Page 258: ...mbol Register Name Reset Value Access 0 13h RSVD Reserved 0h RO 14 17h EPVC0RCTL EP VC 0 Resource Control 800000FFh RO RW 18 9F RSVD Reserved B D F Type 0 0 0 PXPEPBAR Address Offset 14 17h Reset Valu...

Page 259: ...ontrol Register 80000000h RW RO V 3C 3Fh FEDATA_REG Fault Event Data Register 00000000h RW 40 43h FEADDR_REG Fault Event Address Register 00000000h RW 44 47h FEUADDR_REG Fault Event Upper Address Regi...

Page 260: ...er 0000000000 000000h RW 108 10Fh IOTLB_REG IOTLB Invalidate Register 0000000000 000000h RW RO V RW V 110 1FFh RSVD Reserved 0h RO 200 207h RSVD Reserved 0000000000 000000h ROS V 208 20Fh RSVD Reserve...

Page 261: ...apping hardware unit in the platform The maximum number of fault recording registers per remapping hardware unit is 256 39 RO 1b Uncore Page Selective Invalidation PSI 0 Hardware supports only domain...

Page 262: ...s requests to address above 2 x 1 1 from allowed devices return a null Translation Completion Data Entry with R W 0 Guest addressability for a given DMA request is limited to the minimum of the value...

Page 263: ...s supported 4 RO 0b Uncore Required Write Buffer Flushing RWBF 0 No write buffer flushing is needed to ensure changes to memory resident structures are visible to hardware 1 Software must explicitly f...

Page 264: ...t IOTLB invalidation register is calculated as X 16 Y 7 RO V 1b Uncore Snoop Control SC 0 Hardware does not support 1 setting of the SNP field in the page table entries 1 Hardware supports the 1 setti...

Page 265: ...eued invalidations 0 RO 0b Uncore Coherency C This field indicates if hardware access to the root context page table and interrupt remap structures are coherent snooped or not 0 Indicates hardware acc...

Page 266: ...and reflecting the status of the command through the TES field in the Global Status register The value returned on a read of this field is undefined 30 WO 0b Uncore Set Root Table Pointer SRTP Softwar...

Page 267: ...nter must be set in hardware through the SFL field before enabling advanced fault logging Hardware reports the status of the advanced fault logging enable operation through the AFLS field in the Globa...

Page 268: ...g or re enabling after disabling interrupt remapping hardware through the IRE field After a Set Interrupt Remap Table Pointer operation software must globally invalidate the interrupt entry cache This...

Page 269: ...Command register 1 Set by hardware when hardware completes the Set Fault Log Pointer operation using the value provided in the Advanced Fault Log register 28 RO 0b Uncore Advanced Fault Logging Statu...

Page 270: ...enabled and Extended Interrupt Mode x2APIC mode is not enabled 0 Compatibility format interrupts are blocked 1 Compatibility format interrupts are processed as pass through bypassing interrupt remappi...

Page 271: ...invalidation requests pending at this remapping hardware unit Since information from the context cache may be used by hardware to tag IOTLB entries software must perform domain selective or global inv...

Page 272: ...ective invalidations The following encodings are defined for this field 00 No bits in the SID field masked 01 Mask most significant bit of function number in the SID field 10 Mask two most significant...

Page 273: ...received an unexpected or invalid Device IOTLB invalidation completion This could be due to either an invalid ITag or invalid source id in an invalidation completion response At this time a fault even...

Page 274: ...across all the fault recording registers of this remapping hardware unit 0 No pending faults in any of the fault recording registers 1 One or more fault recording registers has pending faults The FRI...

Page 275: ...dware detected error associated with the Invalidation Queue setting the IQE field in the Fault Status register Hardware detected invalid Device IOTLB invalidation completion setting the ICE field in t...

Page 276: ...ing only 16 bit interrupt data may treat this field as RsvdZ 15 0 RW 0000h Uncore Interrupt Message Data IMD Data value in the interrupt request B D F Type 0 0 0 VC0PREMAP Address Offset 40 43h Reset...

Page 277: ...Address FLA This field specifies the base of 4 KB aligned fault log region in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Software specifies t...

Page 278: ...enabled all DMA requests accessing protected memory regions are blocked When DMA remapping is enabled DMA requests processed as pass through Translation Type value of 10b in Context Entry and accessin...

Page 279: ...nds on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding the most significant zero bit position with 0 in the value read back fro...

Page 280: ...e value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The Protected low memory base and limit registers functions as follows Programming the protected low...

Page 281: ...iting all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of this register are decoded by hardware as...

Page 282: ...imit register are decoded by hardware as all 1s The protected high memory Base and Limit registers function as follows Programming the protected low memory base and limit registers with the same value...

Page 283: ...RO V Size 64 bits BIOS Optimal Default 0000000000000h Bit Attr Reset Value RST PWR Description 63 19 RO 0h Reserved 18 4 RO V 0000h Uncore Queue Head QH This field specifies the offset 128 bit aligned...

Page 284: ...0h Reserved 38 12 RW L 0000000h Uncore Invalidation Queue Base Address IQA This field points to the base of 4 KB aligned invalidation request queue Hardware ignores and does not implement bits 63 HAW...

Page 285: ...ield is Set 30 RO V 0b Uncore Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition Interrupt condition is defined as An Invalidation Wait Descriptor with Interrup...

Page 286: ...0 VC0PREMAP Address Offset A4 A7h Reset Value 00000000h Access RW L Size 32 bits Bit Attr Reset Value RST PWR Description 31 16 RW L 0000h Uncore Extended Interrupt Message Data EIMD This field is va...

Page 287: ...0000000000000000h Access RW L Size 64 bits BIOS Optimal Default 00000000h Bit Attr Reset Value RST PWR Description 63 39 RO 0h Reserved 38 12 RW L 0000000h Uncore Interrupt Remapping Table Address IRT...

Page 288: ...n hardware 0 Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware must f...

Page 289: ...n requests when there is a context cache invalidation request pending at this remapping hardware unit Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register...

Page 290: ...f the DRD field is reported as clear in the Capability register When the DRD field is reported as Set in the Capability register the following encodings are supported for this field 0 Hardware may com...

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Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011, Datasheet

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Summary of Contents for 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011

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