Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 2 01-2011, Datasheet

Page: 204 / 290

Processor Configuration Registers
204 Datasheet, Volume 2
2.13 MCHBAR Registers in Memory Controller –
Channel 0
Table 2-15 lists the registers arranged by address offset. Register bit descriptions are in
the sections following the table.
2.13.1 PM_PDWN_config_C0—Power-down Configuration
Register
This register defines the power-down (CKE-off) operation – power-down mode, idle
timer, and global / per rank decision.
Table 2-15. MCHBAR Registers in Memory Controller – Channel 0 Register Address Map
Address
Offset
Register Symbol Register Name
Reset
Value
Access
0–40AFh RSVD Reserved — —
40B0-40B3h PM_PDWN_config_C0 Power-down Configuration 00000000h RW-L
40B4–40C7h RSVD Reserved — —
40D0–438Fh RSVD Reserved — —
4294–4297h TC_RFP_C0 Refresh Timing Parameters 46B41004h RW-L
4298–429Bh TC_RFTP_C0 Refresh Parameters 0000980Fh RW-L
429C–438Fh RSVD Reserved — —
B/D/F/Type: 0/0/0/MCHBAR MC0
Address Offset: 40B0-40B3h
Reset Value: 00000000h
Access: RW-L
Size: 32 bits
BIOS Optimal Default: 00000h
Bit Attr
Reset
Value
RST/
PWR
Description
31:13 RO 0h Reserved
12 RW-L 0b Uncore
Global power-down (GLPDN)
1 = Power-down decision is global for channel.
0 = A separate decision is taken for each rank.
11:0 RO 0h Reserved