Datasheet, Volume 2
41
Processor Configuration Registers
2.3.13.3
Legacy VGA and I/O Range Decode Rules
The legacy 128 KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to
IGD (Device 2), PCI Express (Device 1 functions or Device 6), and/or to the DMI
Interface depending on the programming of the VGA steering bits. Priority for VGA
mapping is constant in that the processor always decodes internally mapped devices
first. Internal to the processor, decode precedence is always given to IGD. The
processor always positively decodes internally mapped devices, namely the IGD.
Subsequent decoding of regions mapped to either PCI Express port or the DMI
Interface depends on the Legacy VGA configurations bits (VGA Enable and MDAP).
For the remainder of this section, PCI Express can refer to either the device 1 port
functions or the device 6 port.
VGA range accesses will always be mapped as UC type memory.
Figure 2-8. PEG Upstream VC0 Memory Map
A0000-BFFFF (VGA)
GMADR
FEE0_0000 – FEEF_FFFF( MSI)
TSEG_BASE
mem writes
non-snoop mem write
mem reads
invalid transaction
mem writes
CPU (IntLogical/IntPhysical)
mem reads
Invalid transaction
mem writes
peer write (if matching PEG range else invalid)
mem reads
Invalid transaction
64GB
REMAPLIMIT
TOLUD
4GB
REMAPBASE
mem writes
Route based on SNR bit.
mem reads
Route based on SNR bit.
TOM = total physical DRAM
Upstream Initiated VC0 Cycle Memory Map
TOLUD-(Gfx Stolen)-(Gfx GTT stolen)
-(TSEG)
TSEG_BASE - DPR
2TB
mem writes
invalid transaction
mem reads
Invalid transaction
TOUUD
