Processor Configuration Registers
38
Datasheet, Volume 2
DMI Interface Accesses to the processor that Cross Device Boundaries
The processor does not support transactions that cross device boundaries. This should
never occur because PCI Express transactions are not allowed to cross a 4 KB
boundary.
For reads, the processor will provide separate completion status for each naturally-
aligned 64 byte block or, if chaining is enabled, each 128 byte block. If the starting
address of a transaction hits a valid address the portion of a request that hits that
target device (PCI Express or DRAM) will complete normally.
If the starting transaction address hits an invalid address, the entire transaction will be
remapped to address 000C_0000h and dispatched to DRAM. A single unsupported
request completion will result.
2.3.13.1.1
TC/VC Mapping Details
• VC0 (enabled by default)
— Snoop port and Non-snoop Asynchronous transactions are supported.
— Internal Graphics GMADR writes can occur. Unlike FSB chipsets, these will NOT
be snooped regardless of the snoop not required (SNR) bit.
— Internal Graphics GMADR reads (unsupported).
— Peer writes can occur. The SNR bit is ignored.
— MSI can occur. These will route and be sent to the cores as
Intlogical/IntPhysical interrupts regardless of the SNR bit.
— VLW messages can occur. These will route and be sent to the cores as VLW
messages regardless of the SNR bit.
— MCTP messages can occur. These are routed in a peer fashion.
• VCp (Optionally enabled)
— Supports priority snoop traffic only. This VC is given higher priority at the snoop
VC arbiter. Routed as an independent virtual channel and treated independently
within the Cache module. VCp snoops are indicated as “high priority” in the
snoop priority field. USB classic and USB2 traffic are expected to use this
channel. Note, on prior chipsets, this was termed “snoop isochronous” traffic.
“Snoop isochronous” is now termed “priority snoop” traffic.
— SNR bit is ignored.
— MSI on VCP is supported.
— Peer read and write requests are not supported. Writes will route to address
000C_0000h with byte enables deasserted, while reads will route to address
000C_0000h and an unsupported request completion.
— Internal Graphics GMADR writes are NOT supported. These will route to
address 000C_0000h with byte enables de-asserted.
— Internal Graphics GMADR reads are not supported.
— See DMI2 TC mapping for expected TC to VCp mapping. This has changed from
DMI to DMI2.
• VC1 (Optionally enabled)
— Supports non-snoop transactions only. (Used for isochronous traffic). Note that
the PCI Express Egress port (PXPEPBAR) must also be programmed
appropriately.
— The snoop not required (SNR) bit must be set. Any transaction with the SNR bit
not set will be treated as an unsupported request.
— MSI and peer transactions will be treated as unsupported requests.
— No “pacer” arbitration or TWRR arbitration will occur. Never remaps to different
port. (PCH takes care of Egress port remapping). The PCH will meter TCm ME
accesses and Azalia TC1 access bandwidth.
— Internal Graphics GMADR writes and GMADR reads are not supported.
