Datasheet, Volume 2
241
Processor Configuration Registers
2.18.23 IECTL_REG—Invalidation Event Control Register
This register specifies the invalidation event interrupt control bits. This register is
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
A0–A3h
Reset Value:
80000000h
Access:
RW-L, RO-V
Size:
32 bits
BIOS Optimal Default
00000000h
Bit
Attr
Reset
Value
RST/
PWR
Description
31
RW-L
1b
Uncore
Interrupt Mask (IM)
0 = No masking of interrupt. When an invalidation event condition
is detected, hardware issues an interrupt message (using the
Invalidation Event Data & Invalidation Event Address register
values).
1 = This is the value on reset. Software may mask interrupt
message generation by setting this field. Hardware is
prohibited from sending the interrupt message when this field
is set.
30
RO-V
0b
Uncore
Interrupt Pending (IP)
Hardware sets the IP bit when it detects an interrupt condition.
Interrupt condition is defined as:
• An Invalidation Wait Descriptor with Interrupt Flag (IF) bit set
completed, setting the IWC field in the Invalidation Completion
Status register.
• If the IWC bit in the Invalidation Completion Status register
was already Set at the time of setting this field, it is not
treated as a new interrupt condition.
The IP bit is kept set by hardware while the interrupt message is
held pending. The interrupt message could be held pending due to
interrupt mask (IM bit) being set, or due to other transient
hardware conditions. The IP bit is cleared by hardware as soon as
the interrupt message pending condition is serviced. This could be
due to either:
• Hardware issuing the interrupt message due to either change
in the transient hardware condition that caused interrupt
message to be held pending or due to software clearing the IM
bit.
• Software servicing the IWC bit in the Invalidation Completion
Status register.
29:0
RO
0h
Reserved
