Infineon TLE9262BQXV33, Manual

Page: 163 / 176

Data Sheet 163 Rev. 1.00
2017-07-31
TLE9262BQXV33
Serial Peripheral Interface
16.7 Electrical Characteristics
Table 30 Electrical Characteristics
V
S
= 5.5 V to 28 V, T
j
= -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
SPI frequency
Maximum SPI frequency f
SPI,max
– – 4.0 MHz
1)
P_16.7.1
SPI Interface; Logic Inputs SDI, CLK and CSN
H-input Voltage Threshold V
IH
– – 0.7*
V
CC1
V – P_16.7.2
L-input Voltage Threshold V
IL
0.3*
V
CC1
– – V – P_16.7.3
Hysteresis of input Voltage V
IHY
0.08 ×
V
CC1
0.12 ×
V
CC1
0.5 ×
V
CC1
V
1)
P_16.7.4
Pull-up Resistance at pin CSN R
ICSN
20 40 80 k Ω V
CSN
= 0.7 x V
CC1
P_16.7.5
Pull-down Resistance at pin
SDI and CLK R
ICLK/SDI
20 40 80 k Ω V
SDI/CLK
=
0.2 x V
CC1
P_16.7.6
Input Capacitance at pin
CSN, SDI or CLK C
I
– 10 – pF
1)
P_16.7.7
Logic Output SDO
H-output Voltage Level V
SDOH
V
CC1
-
0.4
V
CC1
-
0.2
– V I
DOH
= -1.6 mA P_16.7.8
L-output Voltage Level V
SDOL
– 0.2 0.4 V I
DOL
= 1.6 mA P_16.7.9
Tristate Leakage Current I
SDOLK
-10 – 10 µA V
CSN
= V
CC1
;
0 V < V
DO
< V
CC1
P_16.7.10
Tristate Input Capacitance C
SDO
– 10 15 pF
1)
P_16.7.11
Data Input Timing
1)
Clock Period t
pCLK
250 – – ns – P_16.7.12
Clock High Time t
CLKH
125 – – ns – P_16.7.13
Clock Low Time t
CLKL
125 – – ns – P_16.7.14
Clock Low before CSN Low t
bef
125 – – ns – P_16.7.15
CSN Setup Time t
lead
250 – – ns – P_16.7.16
CLK Setup Time t
lag
250 – – ns – P_16.7.17
Clock Low after CSN High t
beh
125 – – ns – P_16.7.18
SDI Set-up Time t
DISU
100 – – ns – P_16.7.19
SDI Hold Time t
DIHO
50 – – ns – P_16.7.20
Input Signal Rise Time at pin
SDI, CLK and CSN t
rIN
– – 50 ns – P_16.7.21