Data Sheet
134
Rev. 1.00
2017-07-31
TLE9262BQXV33
Serial Peripheral Interface
Notes
1. Clearing the FO_ON bit will not disable the FOx outputs for the case a failure occurred which triggered the FOx
outputs. In this case the FOx outputs have to be disabled by clearing the FAILURE bit.
HW_CTRL
Mode- and Supply Control (Address 000 0010
B
)
POR / Soft Reset Value: y000 y000
B
;
Restart Value: xx0x x00x
B
7
6
5
4
3
2
1
0
VCC3_V_CFG SOFT_RESET
_RO
FO_ON
VCC3_VS_UV
_OFF
VCC3_LS
Reserved
VCC3_LS_ST
P_ON
CFG
r
rw
rw rwh
rw
rw
r
rw
rw
Field
Bits
Type
Description
VCC3_
V_CFG
7
rw
VCC3 Output Voltage Configuration (if configured as
independent voltage regulator)
0B , VCC3 has same output voltage as VCC1
1B , VCC3 is configured to either 3.3V or 1.8V (depending on VCC1
derivative)
SOFT_
RESET_RO
6
rw
Soft Reset Configuration
0B , RO will be triggered (pulled low) during a Soft Reset
1B , No RO triggering during a Soft Reset
FO_ON
5
rwh
Failure Output Activation (FO1..3)
0B , FOx not activated by software, FO can be activated by
defined failures (see
Chapter 14
)
1B , FOx activated by software (via SPI)
VCC3_VS_
UV_OFF
4
rw
VCC3 VS_UV shutdown configuration
0B , VCC3 will be disabled automatically at VS_UV
1B , VCC3 will stay enabled even below VS_UV
VCC3_LS
3
rw
VCC3 Configuration
0B , VCC3 operating as a stand-alone regulator
1B , VCC3 in load sharing operation with VCC1
Reserved
2
r
Reserved, always reads as 0
VCC3_LS_
STP_ON
1
rw
VCC3 Load Sharing in SBC Stop Mode configuration
0B , VCC3 in LS configuration during SBC Stop Mode and high-
power mode: disabled
1B , VCC3 in LS configuration during SBC Stop Mode and high-
power mode: enabled
CFG
0
rw
Configuration Select (see also
Table 5
)
0B , Depending on hardware configuration, SBC Restart or Fail-
Safe Mode is reached after the 2. watchdog trigger failure
(=default) - Config 3/4
1B , Depending on hardware configuration, SBC Restart or Fail-
Safe Mode is reached after the 1. watchdog trigger failure -
Config 1/2